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    HUMIDITY CONTROL IN CHEMICAL REACTORS
    17.
    发明申请
    HUMIDITY CONTROL IN CHEMICAL REACTORS 审中-公开
    化学反应器中的湿度控制

    公开(公告)号：US20140120609A1

    公开(公告)日：2014-05-01

    申请号：US14064021

    申请日：2013-10-25

    Applicant: Massachusetts Institute of Technology

    Inventor： Shireen Goh ,  Rajeev Jagga Ram ,  Kevin Shao-Kwan Lee ,  Michelangelo Canzoneri ,  Horst Blum

    IPC: C12M1/34

    Abstract: Control of humidity in chemical reactors, and associated systems and methods, are generally described. In certain embodiments, the humidity within gas transport conduits and chambers can be controlled to inhibit unwanted condensation within gas transport pathways. By inhibiting condensation within gas transport pathways, clogging of such pathways can be limited (or eliminated) such that transport of gas can be more easily and controllably achieved. In addition, strategies for purging condensed liquid from chemical reactor systems are also described.

    Abstract translation: 通常描述化学反应器中的湿度控制以及相关系统和方法。 在某些实施例中，可以控制气体输送导管和腔室内的湿度以抑制气体输送路径内的不需要的冷凝。 通过抑制气体输送通道内的冷凝，可以限制（或消除）这种途径的堵塞，使得气体的输送可以更容易和可控地实现。 此外，还描述了用于从化学反应器系统中吹扫冷凝液体的策略。

    Semiconductor devices with curved-shape silicon germanium structures and optical resonator structures
    18.
    发明授权
    Semiconductor devices with curved-shape silicon germanium structures and optical resonator structures 有权

    公开(公告)号：US10978608B2

    公开(公告)日：2021-04-13

    申请号：US16376086

    申请日：2019-04-05

    Applicant: Massachusetts Institute of Technology

    Inventor： Luca Alloatti ,  Rajeev Jagga Ram ,  Dinis Cheian

    IPC: H01L27/14 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/103 ,  G02B6/12 ,  G02B6/293 ,  H01L31/0224 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/11

    Abstract: Semiconductor devices, such as photonics devices, employ substantially curved-shaped Silicon-Germanium (SiGe) structures and are fabricated using zero-change CMOS fabrication process technologies. In one example, a closed-loop resonator waveguide-coupled photodetector includes a silicon resonator structure formed in a silicon substrate, interdigitated n-doped well-implant regions and p-doped well-implant regions forming multiple silicon p-n junctions around the silicon resonator structure, and a closed-loop SiGe photocarrier generation region formed in a pocket within the interdigitated n-doped and p-doped well implant regions. The closed-loop SiGe region is located so as to substantially overlap with an optical mode of radiation when present in the silicon resonator structure, and traverses the multiple silicon p-n junctions around the silicon resonator structure. Electric fields arising from the respective p-n silicon junctions significantly facilitate a flow of the generated photocarriers between electric contact regions of the photodetector.

    Waveguide formation using CMOS fabrication techniques
    19.
    发明授权
    Waveguide formation using CMOS fabrication techniques 有权

    公开(公告)号：US10768368B2

    公开(公告)日：2020-09-08

    申请号：US16680630

    申请日：2019-11-12

    Applicant: Massachusetts Institute of Technology

    Inventor： Jason Scott Orcutt ,  Karan Kartik Mehta ,  Rajeev Jagga Ram ,  Amir Hossein Atabaki

    IPC: G02B6/13 ,  G02B6/136 ,  G02B6/12 ,  G02B6/132 ,  G02B6/122 ,  G02F1/01 ,  G02F1/025 ,  G02B6/30 ,  G02F1/015

    Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

    WAVEGUIDE FORMATION USING CMOS FABRICATION TECHNIQUES
    20.
    发明申请
    WAVEGUIDE FORMATION USING CMOS FABRICATION TECHNIQUES 审中-公开

    公开(公告)号：US20200081184A1

    公开(公告)日：2020-03-12

    申请号：US16680630

    申请日：2019-11-12

    Applicant: Massachusetts Institute of Technology

    Inventor： Jason Scott ORCUTT ,  Karan Kartik MEHTA ,  Rajeev Jagga Ram ,  Amir Hossein ATABAKI

    IPC: G02B6/136 ,  G02F1/025 ,  G02F1/01 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

    Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

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