公开(公告)号：US20200081184A1

公开(公告)日：2020-03-12

申请号：US16680630

申请日：2019-11-12

Applicant: Massachusetts Institute of Technology

Inventor： Jason Scott ORCUTT ,  Karan Kartik MEHTA ,  Rajeev Jagga Ram ,  Amir Hossein ATABAKI

IPC: G02B6/136 ,  G02F1/025 ,  G02F1/01 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.