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    Sigma-delta modulators with excess loop delay compensation
    11.
    发明授权
    Sigma-delta modulators with excess loop delay compensation 有权
    具有多余环路延迟补偿的Σ-Δ调制器

    公开(公告)号：US08791848B2

    公开(公告)日：2014-07-29

    申请号：US13760379

    申请日：2013-02-06

    Applicant: MediaTek Inc.

    Inventor： Chen-Yen Ho ,  Chi-Lun Lo ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

    IPC: H03M3/00

    CPC classification number: H03M3/458 ,  H03M3/37 ,  H03M3/454

    Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator includes a multi-stage loop filter, a quantizer, and a digital-to-analog converter. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. Each stage of the multi-stage loop filter includes a feedback network. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. The digital-to-analog converter receives the digital output signal and converts the digital output signal to a compensation signal. The digital-to-analog converter provides the compensation signal to a plurality of internal nodes in the feedback network of the last stage of the multi-stage loop filter.

    Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器，量化器和数模转换器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 多级环路滤波器的每一级都包括反馈网络。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 数模转换器接收数字输出信号并将数字输出信号转换成补偿信号。 数模转换器向多级环路滤波器的最后级的反馈网络中的多个内部节点提供补偿信号。

    PROCESS-VOLTAGE SENSOR WITH SMALLER CHIP AREA
    12.
    发明申请
    PROCESS-VOLTAGE SENSOR WITH SMALLER CHIP AREA 有权

    公开(公告)号：US20240410920A1

    公开(公告)日：2024-12-12

    申请号：US18663101

    申请日：2024-05-14

    Applicant: MEDIATEK INC.

    Inventor： Yi-Ta Lin ,  Hung-Chieh Tsai

    IPC: G01R19/00 ,  G01R35/00

    Abstract: The present invention provides a PV sensor including a control circuit, a RC calibration circuit, and a voltage sensor. The control circuit is configured to generate at least one control signal. The RC calibration circuit is configured to receive the at least one control signal to generate a voltage indicates information of (1/R*C). The voltage sensor comprises a comparator, wherein the voltage sensor senses a voltage level of a received signal by using comparator to generate a sensing result, and the comparator is further configured to compare the calibration result within a reference voltage to generate a comparison result to the control circuit.

    Filters with order enhancement
    15.
    发明授权
    Filters with order enhancement 有权
    具有订单增强功能的过滤器

    公开(公告)号：US08810308B2

    公开(公告)日：2014-08-19

    申请号：US13758028

    申请日：2013-02-04

    Applicant: MediaTek Inc.

    Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Chi-Lun Lo ,  Chen-Yen Ho

    IPC: H03K5/00 ,  H03H11/12

    CPC classification number: H03H11/1204 ,  H03H11/1252 ,  H03H11/126

    Abstract: A filter is provided. The filter receives an input signal and generates an output signal according to the input signal. The filter includes an input network, a high-pass network, and an operational circuit. The first input network provides a first normal path for the input signal to generate a first normal signal. The first high-pass network provides a first high-pass path for the input signal to generate a first high-pass signal. The operational circuit has first and second input terminals. The polarity of the second input terminal is inverse to that of the first input terminal. The operational circuit receives the first normal signal by the first input terminal and the first high-pass signal by the second input terminal such that a subtraction operation is performed on the first normal signal and the first high-pass filter to accomplish a low-pass filtering operation for generating the output signal.

    Abstract translation: 提供了一个过滤器。 滤波器接收输入信号，并根据输入信号产生输出信号。 滤波器包括输入网络，高通网络和操作电路。 第一输入网络为输入信号提供第一正常路径以产生第一正常信号。 第一高通网络为输入信号提供第一高通路径以产生第一高通信号。 该操作电路具有第一和第二输入端。 第二输入端子的极性与第一输入端子的极性相反。 操作电路由第一输入端接收第一正常信号和由第二输入端接收第一高通信号，使得对第一正常信号和第一高通滤波器执行减法运算以完成低通 用于产生输出信号的滤波操作。

    SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER AND RELATED SIGMA-DELTA MODULATION METHOD
    16.
    发明申请
    SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER AND RELATED SIGMA-DELTA MODULATION METHOD 有权
    具有SAR ADC和TRANCATER的SIGMA-DELTA调制器及相关SIGMA-DELTA调制方法

    公开(公告)号：US20130088376A1

    公开(公告)日：2013-04-11

    申请号：US13691860

    申请日：2012-12-03

    Applicant: Mediatek Inc.

    Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

    Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

    Abstract translation: Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息。

    Reference voltage buffer with settling enhancement
    17.
    发明授权
    Reference voltage buffer with settling enhancement 有权

    公开(公告)号：US11233513B2

    公开(公告)日：2022-01-25

    申请号：US17065526

    申请日：2020-10-08

    Applicant: MEDIATEK INC.

    Inventor： Hung-Chieh Tsai ,  Sheng-Hui Liao

    IPC: G05F1/10 ,  G05F3/02 ,  H03K19/0185 ,  G05F3/24

    Abstract: The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.

    Amplifier, fully-differential amplifier and delta-sigma modulator
    20.
    发明授权
    Amplifier, fully-differential amplifier and delta-sigma modulator 有权
    放大器，全差分放大器和Δ-Σ调制器

    公开(公告)号：US09007249B2

    公开(公告)日：2015-04-14

    申请号：US14134944

    申请日：2013-12-19

    Applicant: MediaTek Inc.

    Inventor： Chen-Yen Ho ,  Chi-Lun Lo ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

    IPC: H03M3/00 ,  H03F3/45 ,  H03F3/26 ,  H03F3/30

    CPC classification number: H03F1/0205 ,  H03F3/265 ,  H03F3/30 ,  H03F3/3023 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/18 ,  H03F2203/30021 ,  H03F2203/30033 ,  H03F2203/45022 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03M3/39 ,  H03M3/50

    Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; and a resistance component, coupling the gate of the first transistor to a bias voltage level.

    Abstract translation: 放大器包括前端增益级和AC耦合推挽输出级。 AC耦合推挽输出级包括具有源极，漏极和栅极的第一晶体管，其中第一晶体管的源极耦合到第一电压电平; 具有源极，漏极和栅极的第二晶体管，其中所述第二晶体管的源极耦合到第二电压电平，所述第二晶体管的栅极耦合到所述前端增益级，并且所述漏极 第二晶体管耦合到第一晶体管的漏极，以形成放大器的输出端; AC耦合电容器，其是耦合在前端增益级与第一晶体管的栅极之间的无源双端电气元件; 以及电阻分量，将第一晶体管的栅极耦合到偏置电压电平。

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