Detection and decoding in flash memories with selective binary and non-binary decoding
    12.
    发明授权
    Detection and decoding in flash memories with selective binary and non-binary decoding 有权
    在具有选择性二进制和非二进制解码的闪存中进行检测和解码

    公开(公告)号:US09086984B2

    公开(公告)日:2015-07-21

    申请号:US13755717

    申请日:2013-01-31

    CPC classification number: G06F11/1008 G06F11/1048 G11C8/12 G11C11/5621

    Abstract: Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently.

    Abstract translation: 提供了用于具有选择性二进制和非二进制解码的闪存中的检测和解码的方法和装置。 来自闪存设备的数据通过从闪存设备的一个或多个页面获得多个位的一个或多个读取值来处理; 转换 基于当从多个比特读取特定模式时将给定数据模式写入多个比特的概率,将所述多个比特的一个或多个读取值提高为非二进制对数似然比; 并使用非二进制对数似然比联合解码多个比特,其中页面被独立编码。

    SYSTEM AND METHOD TO INTERLEAVE MEMORY
    13.
    发明申请
    SYSTEM AND METHOD TO INTERLEAVE MEMORY 有权
    用于记忆的系统和方法

    公开(公告)号:US20150154114A1

    公开(公告)日:2015-06-04

    申请号:US14169424

    申请日:2014-01-31

    CPC classification number: G06F12/0607 G11C7/1012 G11C7/1042

    Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.

    Abstract translation: 存储器交错装置包括第一和第二交织器。 第一交织器响应于扇区选择信号选择性地交织存储在第一存储器中的信息。 第二交织器响应于扇区选择信号选择性地交织存储在第二存储器中的信息。 第一交织器与第二交织器耦合。 存储器交错系统包括交织器和存储装置。 交织器与第一扇区尺寸和第二扇区尺寸相关联。 交织器响应于扇区选择信号选择性地交织存储在第一存储器和/或第二存储器中的信息。 存储装置响应于扇区选择信号选择性地向交织器提供第一掩蔽种子和/或第二掩蔽种子。 还公开了相应的方法。

    Memory Architecture for Layered Low-Density Parity-Check Decoder
    17.
    发明申请
    Memory Architecture for Layered Low-Density Parity-Check Decoder 有权
    分层低密度奇偶校验解码器的内存架构

    公开(公告)号:US20140223259A1

    公开(公告)日:2014-08-07

    申请号:US13760609

    申请日:2013-02-06

    Abstract: A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.

    Abstract translation: LE硬判决存储器包括用于交织来自第一和第二循环的L值的全局映射元素,并将交错值存储在第一存储器元件中。 然后,低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。

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