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    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS
    2.
    发明申请
    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS 有权
    信号处理电路由分钟控制的FRONTEND和后端电路

    公开(公告)号：US20140181570A1

    公开(公告)日：2014-06-26

    申请号：US13724946

    申请日：2012-12-21

    申请人： LSI CORPORATION

    发明人： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

    IPC分类号： G06F1/06

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F1/206

    摘要： An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

    摘要翻译： 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

    Slice Formatting and Interleaving for Interleaved Sectors
    3.
    发明申请
    Slice Formatting and Interleaving for Interleaved Sectors 有权
    切片扇区的切片格式和交错

    公开(公告)号：US20150161045A1

    公开(公告)日：2015-06-11

    申请号：US14153154

    申请日：2014-01-13

    申请人： LSI Corporation

    发明人： Qi Zuo ,  Kuhong Jeong ,  Shu Li ,  Xiang Wang ,  Han Fang ,  Shaohua Yang

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0607

    摘要： A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

    摘要翻译： 公开了一种用于在存储系统中交织多个逻辑扇区的存储系统和方法。 该方法包括：将每个逻辑扇区划分成预定数量的片; 顺序索引逻辑扇区，其中每个逻辑扇区由逻辑扇区索引标识; 顺序索引每个逻辑扇区中的预定数量的片，其中预定数量片的每个片由每个逻辑扇区内的片索引识别; 以及根据片交织处理对逻辑扇区进行交织。 交错步骤还包括：a）将第一索引逻辑扇区的第一索引片段识别为初始片段; 以及b）通过将切片索引推进到切片索引序列中的后续索引并且将逻辑扇区索引推进到逻辑扇区索引序列中的后续索引来识别随后的片段。

    System and Method for Elastic Despreader Memory Management
    4.
    发明申请
    System and Method for Elastic Despreader Memory Management 审中-公开
    弹性解扩器内存管理系统与方法

    公开(公告)号：US20150269097A1

    公开(公告)日：2015-09-24

    申请号：US14230908

    申请日：2014-03-31

    申请人： LSI Corporation

    发明人： Ku Hong Jeong ,  Qi Zuo ,  Shaohua Yang ,  Kaitlyn T. Nguyen

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1673 ,  G06F5/12 ,  G06F5/14 ,  H04L49/9005 ,  H04L49/9031 ,  H04L49/9036

    摘要： The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing. To prevent buffer overflow or degraded decoder performance, the memory availability of the buffer is monitored, and transfers are suspended when the memory availability of the buffer is below a threshold buffer availability.

    摘要翻译： 本公开涉及一种管理通信信道中的存储器资源的系统和方法。 根据各种实施例，与多个数据扇区相关联的输入存储器片段被解交织并且顺序地通过缓冲器传送到解码器用于进一步处理。 为了防止缓冲区溢出或解码器性能下降，缓冲区的内存可用性受到监控，当缓冲区的内存可用性低于阈值缓冲区可用性时，传输将被暂停。

    Low Density Parity Check Decoder With Relative Indexing
    6.
    发明申请
    Low Density Parity Check Decoder With Relative Indexing 审中-公开
    具有相对索引的低密度奇偶校验解码器

    公开(公告)号：US20160020783A1

    公开(公告)日：2016-01-21

    申请号：US14334125

    申请日：2014-07-17

    申请人： LSI Corporation

    发明人： Shaohua Yang ,  Shu Li ,  Dan Liu ,  Qi Zuo

    IPC分类号： H03M13/11 ,  G11B20/10 ,  G11B20/18

    CPC分类号： H03M13/114 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1108 ,  H03M13/1122 ,  H03M13/116 ,  H03M13/451 ,  H03M13/458 ,  H03M13/6325 ,  H03M13/6577 ,  H03M13/658

    摘要： An apparatus for low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to update variable node values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages based on the variable node to check node messages. The variable node processor and the check node processor comprise a quasi-cyclic decoder with relative indexes that refer to non-zero circulants.

    摘要翻译： 用于低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点将可变节点值更新到可变节点消息。 校验节点处理器可操作以基于变量节点向可变节点消息生成校验节点，以校验节点消息。 可变节点处理器和校验节点处理器包括具有参考非零循环的相对索引的准循环解码器。

    Shift register-based layered low density parity check decoder
    7.
    发明授权
    Shift register-based layered low density parity check decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US09048867B2

    公开(公告)日：2015-06-02

    申请号：US13898685

    申请日：2013-05-21

    申请人： LSI Corporation

    发明人： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC分类号： H03M13/11 ,  H04L1/00

    CPC分类号： H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    摘要： An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    摘要翻译： 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

    Shift Register-Based Layered Low Density Parity Check Decoder
    8.
    发明申请
    Shift Register-Based Layered Low Density Parity Check Decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US20140351671A1

    公开(公告)日：2014-11-27

    申请号：US13898685

    申请日：2013-05-21

    申请人： LSI Corporation

    发明人： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    摘要： An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    摘要翻译： 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

    Signal processing circuitry with frontend and backend circuitry controlled by separate clocks
    9.
    发明授权
    Signal processing circuitry with frontend and backend circuitry controlled by separate clocks 有权
    信号处理电路，前端和后端电路由单独的时钟控制

    公开(公告)号：US08773799B1

    公开(公告)日：2014-07-08

    申请号：US13724946

    申请日：2012-12-21

    申请人： LSI Corporation

    发明人： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

    IPC分类号： G11B5/09

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F1/206

    摘要： An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

    摘要翻译： 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

    Slice formatting and interleaving for interleaved sectors
    10.
    发明授权
    Slice formatting and interleaving for interleaved sectors 有权
    交错扇区的切片格式化和交织

    公开(公告)号：US09304910B2

    公开(公告)日：2016-04-05

    申请号：US14153154

    申请日：2014-01-13

    申请人： LSI Corporation

    发明人： Qi Zuo ,  Kuhong Jeong ,  Shu Li ,  Xiang Wang ,  Han Fang ,  Shaohua Yang

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0607

    摘要： A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

    摘要翻译： 公开了一种用于在存储系统中交织多个逻辑扇区的存储系统和方法。 该方法包括：将每个逻辑扇区划分成预定数量的片; 顺序索引逻辑扇区，其中每个逻辑扇区由逻辑扇区索引标识; 顺序索引每个逻辑扇区中的预定数量的片，其中预定数量片的每个片由每个逻辑扇区内的片索引识别; 以及根据片交织处理对逻辑扇区进行交织。 交错步骤还包括：a）将第一索引逻辑扇区的第一索引片段识别为初始片段; 以及b）通过将切片索引推进到切片索引序列中的后续索引并且将逻辑扇区索引推进到逻辑扇区索引序列中的后续索引来识别随后的片段。