-
公开(公告)号:US20230402507A1
公开(公告)日:2023-12-14
申请号:US17838637
申请日:2022-06-13
Applicant: Intel Corporation
Inventor: Rohit Galatage , Willy Rachmady , Cheng-Ying Huang , Jami A. Wiedemer , Munzarin F. Qayyum , Nicole K. Thomas , Patrick Morrow , Marko Radosavljevic , Mauro J. Kobrinsky
IPC: H01L29/06 , H01L27/092 , H01L29/423 , H01L29/417 , H01L29/786
CPC classification number: H01L29/0673 , H01L27/0924 , H01L29/42392 , H01L29/41733 , H01L29/78618 , H01L29/78696
Abstract: An integrated circuit structure includes a second device stacked vertically above a first device. The first device includes (i) a first source or drain region, (ii) a first source or drain contact coupled to the first source or drain region, and (iii) a first layer comprising a first metal and first one or more semiconductor materials between at least a section of the first source or drain region and the first source or drain contact. The second device includes (i) a second source or drain region, (ii) a second source or drain contact coupled to the second source or drain region, and (iii) a second layer comprising a second metal and second one or more semiconductor materials between at least a section of the second source or drain region and the second source or drain contact. In an example, the first metal and the second metal are different.
-
12.
公开(公告)号:US20230395678A1
公开(公告)日:2023-12-07
申请号:US17831802
申请日:2022-06-03
Applicant: Intel Corporation
Inventor: Munzarin F. Qayyum , Nicole K. Thomas , Jami A. Wiedemer , Jack T. Kavalieros , Marko Radosavljevic , Willy Rachmady , Cheng-Ying Huang , Rohit Galatage , Nitesh Kumar , Kai Loon Cheong , Venkata Vasiraju
IPC: H01L29/423 , H01L29/06 , H01L29/786 , H01L29/417 , H01L27/092
CPC classification number: H01L29/42392 , H01L29/0673 , H01L29/78618 , H01L29/78696 , H01L29/41733 , H01L27/0924
Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.
-
公开(公告)号:US11664452B2
公开(公告)日:2023-05-30
申请号:US17085981
申请日:2020-10-30
Applicant: Intel Corporation
Inventor: Pratik A. Patel , Mark Y. Liu , Jami A. Wiedemer , Paul A. Packan
IPC: H01L29/78 , H01L29/66 , H01L21/225 , H01L21/324 , H01L29/08 , H01L29/24 , H01L29/267
CPC classification number: H01L29/7848 , H01L21/2253 , H01L21/324 , H01L29/0847 , H01L29/24 , H01L29/267 , H01L29/66492 , H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/785 , H01L29/7851
Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.
-
-