Memory configuration apparatus, systems, and methods
    12.
    发明申请
    Memory configuration apparatus, systems, and methods 失效
    内存配置设备,系统和方法

    公开(公告)号:US20050223155A1

    公开(公告)日:2005-10-06

    申请号:US10815173

    申请日:2004-03-30

    Applicant: Inching Chen

    Inventor: Inching Chen

    CPC classification number: G06F12/04 G06F12/0646 Y02D10/13

    Abstract: An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as well as methods and articles, may operate to select a memory access group size of about 2N memory banks responsive to receiving an indication of a change in a protocol type, wherein the group is selected from a number B of banks, and N is associated with the protocol type.

    Abstract translation: 装置和系统以及方法和文章可以操作以响应于诸如使用的数据处理单元的协议指示来控制耦合到多个数据处理单元的存储器的带宽。 在一些实施例中,装置和系统以及方法和物品可以操作以响应于接收到协议类型的变化的指示来选择大约2个N个存储体的存储器存取组大小, 其中所述组是从数量B的组中选择的,并且N与所述协议类型相关联。

    Multi-media window manager
    13.
    发明授权
    Multi-media window manager 失效
    多媒体窗口管理器

    公开(公告)号:US5276437A

    公开(公告)日:1994-01-04

    申请号:US872739

    申请日:1992-04-22

    CPC classification number: G09G5/14 G09G2340/125

    Abstract: An apparatus and method for displaying non-obscured pixels in a multiple-media motion video environment (dynamic image management) possessing overlaid windows. In an encoding process, only boundary values and identification values corresponding to each window on a screen are saved in memory of a hardware device. In a decoding process, the hardware device utilizes these initial boundary values saved in memory in such a way that when incoming video data enters the hardware device, the hardware device need only compare the incoming video data's identification with the identification saved in memory. The hardware device includes: compare logic devices, counters, minimal memory devices, a control logic block, and a driver.

    Abstract translation: 一种在具有重叠窗口的多媒体运动视频环境(动态图像管理)中显示非遮蔽像素的装置和方法。 在编码处理中,仅将对应于屏幕上的每个窗口的边界值和识别值保存在硬件设备的存储器中。 在解码过程中,硬件设备利用存储在存储器中的这些初始边界值,使得当输入的视频数据进入硬件设备时,硬件设备只需要将输入的视频数据的标识与保存在存储器中的标识进行比较。 硬件设备包括:比较逻辑器件,计数器,最小存储器件,控制逻辑块和驱动器。

    Method and Apparatus for Manipulating MPEG Video
    16.
    发明申请
    Method and Apparatus for Manipulating MPEG Video 审中-公开
    用于操作MPEG视频的方法和装置

    公开(公告)号:US20130003862A1

    公开(公告)日:2013-01-03

    申请号:US13611208

    申请日:2012-09-12

    Applicant: Inching Chen

    Inventor: Inching Chen

    Abstract: A computer implemented method of manipulating and displaying an MPEG stream is described. In one embodiment of the invention, a computer implemented method comprises defining a spatial location across a series of pictures of an MPEG stream; and for each picture of the series of pictures in the MPEG stream, partially decoding the picture to determine an area of the picture falling within the spatial location.

    Abstract translation: 描述了一种操作和显示MPEG流的计算机实现的方法。 在本发明的一个实施例中,一种计算机实现的方法包括:跨MPEG流的一系列图片定义空间位置; 并且对于MPEG流中的一系列图像的每个图像,部分地解码图像以确定落在空间位置内的图像的区域。

    Method and apparatus for data synchronization
    17.
    发明申请
    Method and apparatus for data synchronization 有权
    用于数据同步的方法和装置

    公开(公告)号:US20090003462A1

    公开(公告)日:2009-01-01

    申请号:US11821866

    申请日:2007-06-26

    Applicant: Inching Chen

    Inventor: Inching Chen

    CPC classification number: H04N21/4384 H04N7/167 H04N21/434 H04N21/4382

    Abstract: In one embodiment of the invention, a memory receives unsynchronized data and a processor performs symbol interleaving at a synchronization point located after a beginning of a superframe.

    Abstract translation: 在本发明的一个实施例中,存储器接收非同步数据,并且处理器在位于超帧开始之后的同步点执行符号交织。

    General purpose micro-coded accelerator
    20.
    发明申请
    General purpose micro-coded accelerator 审中-公开
    通用微码加速器

    公开(公告)号:US20060107027A1

    公开(公告)日:2006-05-18

    申请号:US10987327

    申请日:2004-11-12

    CPC classification number: G06F15/7867 Y02D10/12 Y02D10/13

    Abstract: A micro-coded accelerator may comprise multiple programmable control units, multiple special function units, a cross-bar switch to connect any of the control units to any one or more of the special function units, and a global memory to facilitate processing by these units. Each control unit may have an array of programmable logic arrays (ARPLAs), each of which may be configured in various ways, a local memory, and a switch circuit to enable the components of the control unit to perform various operations. By configuring the ARPLAs, the control units' internal switch circuitry, and the cross-bar switch, the micro-coded accelerator may be dynamically reconfigured to perform multiple types of operations.

    Abstract translation: 微编码加速器可以包括多个可编程控制单元,多个特殊功能单元,将任何控制单元连接到任何一个或多个特殊功能单元的交叉开关,以及一个全局存储器,以便于这些单元进行处理 。 每个控制单元可以具有可编程逻辑阵列(ARPLA)阵列,每个可编程逻辑阵列(ARPLA)可以以各种方式配置,本地存储器和开关电路,以使得控制单元的组件能够执行各种操作。 通过配置ARPLA,控制单元的内部交换电路和交叉开关,可以动态地重新配置微编码加速器以执行多种类型的操作。

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