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公开(公告)号：US20240126507A1
公开(公告)日：2024-04-18
申请号：US18544313
申请日：2023-12-18
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Jonas Olof Gunnar KALLEN , Casper Van Benthem
Abstract: Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
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公开(公告)号：US11954456B2
公开(公告)日：2024-04-09
申请号：US18140571
申请日：2023-04-27
Applicant: Imagination Technologies Limited
Inventor： Jonas Kallen , Sam Elliott
CPC classification number: G06F7/556 , G06F7/4873 , G06F7/727
Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0: m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of [log2 M]; and more than M−2u of the subset of modulo units are arranged at the maximal delay of [log2 M], where 2u is the power of 2 immediately smaller than M.
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13.发明公开公开(公告)号：US20240005073A1
公开(公告)日：2024-01-04
申请号：US18369338
申请日：2023-09-18
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Robert McKemey , Max Freiburghaus
IPC: G06F30/3323
CPC classification number: G06F30/3323 , G06F2119/16
Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.
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14.发明授权公开(公告)号：US11853716B2
公开(公告)日：2023-12-26
申请号：US17538676
申请日：2021-11-30
Applicant: Imagination Technologies Limited
Inventor： Casper Van Benthem , Sam Elliott
CPC classification number: G06F7/483 , G06F7/49947 , G06F7/49963 , G06F7/552 , G06F7/5525 , G06F2207/5521
Abstract: Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.
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公开(公告)号：US11663385B2
公开(公告)日：2023-05-30
申请号：US17478739
申请日：2021-09-17
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F30/3323 , G06F30/367 , G06F30/398 , G06F30/3308 , G06F30/323 , G01R31/00 , G01R31/3183
CPC classification number: G06F30/3323 , G01R31/318357 , G06F30/323 , G06F30/3308 , G06F30/367 , G06F30/398
Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.
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Patent Agency Ranking
公开(公告)号：US10984162B2
公开(公告)日：2021-04-20
申请号：US16896388
申请日：2020-06-09
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F17/50 , G01R31/00 , G06F30/3323 , G01R31/3183 , G06F30/367 , G06F30/398 , G06F30/3308
Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).
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17.发明申请公开(公告)号：US20200302104A1
公开(公告)日：2020-09-24
申请号：US16896388
申请日：2020-06-09
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F30/3323 , G01R31/3183
Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).
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公开(公告)号：US20190258765A1
公开(公告)日：2019-08-22
申请号：US16399218
申请日：2019-04-30
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Sam Elliott
IPC: G06F17/50
Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
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19.发明授权公开(公告)号：US12197835B2
公开(公告)日：2025-01-14
申请号：US18369338
申请日：2023-09-18
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Robert McKemey , Max Freiburghaus
IPC: G06F30/3323 , G06F119/16
Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.
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公开(公告)号：US11829694B2
公开(公告)日：2023-11-28
申请号：US18076338
申请日：2022-12-06
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Rachel Edmonds
IPC: G06F30/3323 , G06F30/392 , G06F111/04
CPC classification number: G06F30/3323 , G06F30/392 , G06F2111/04
Abstract: A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.
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