公开(公告)号：US11239115B2

公开(公告)日：2022-02-01

申请号：US16669231

申请日：2019-10-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Veeraraghavan Basker ,  Alexander Reznicek ,  Junli Wang

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311

Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.

公开(公告)号：US11183558B2

公开(公告)日：2021-11-23

申请号：US16785899

申请日：2020-02-10

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Veeraraghavan Basker ,  Alexander Reznicek ,  Junli Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a nanosheet stack over a portion of a substrate. A first source or drain (S/D) trench is formed adjacent to a first end of the nanosheet stack. A second S/D trench is formed adjacent to a second end of the nanosheet stack. A region of the substrate is removed to form a bottom dielectric isolation (BDI) cavity in the substrate, wherein the BDI cavity is positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench. The BDI cavity is filled with a dielectric material, thereby forming a BDI region positioned beneath at least the nanosheet stack, the first S/D trench, and the second S/D trench.

公开(公告)号：US20210111028A1

公开(公告)日：2021-04-15

申请号：US16598065

申请日：2019-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Veeraraghavan Basker ,  Juntao LI

IPC: H01L21/28 ,  H01L27/11 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

公开(公告)号：US20170069549A1

公开(公告)日：2017-03-09

申请号：US14845448

申请日：2015-09-04

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8238 ,  H01L29/10 ,  H01L21/762 ,  H01L29/167 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31051 ,  H01L21/31056 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/66803

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

Abstract translation: 一种技术涉及形成自对准场效应晶体管。 一种起动穿孔止动器，包括一个其上形成有多个翅片的基片，一个n型场效应晶体管（NFET）区，一个p型场效应晶体管（PFET）区，以及一个具有边界缺陷的中心区 首先提供NFET区域和PFET区域的界面。 然后对场效应晶体管进行掩模以掩蔽NFET区域和PFET区域，使得中心区域被暴露。 然后通过蚀刻中心区域形成中心边界区域以去除边界缺陷。

公开(公告)号：US11862710B2

公开(公告)日：2024-01-02

申请号：US17569669

申请日：2022-01-06

Applicant: International Business Machines Corporation

Inventor： Chun-Chen Yeh ,  Alexander Reznicek ,  Veeraraghavan Basker ,  Junli Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/223 ,  H01L29/06

CPC classification number: H01L29/66666 ,  H01L21/2236 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7827 ,  H01L29/7834

Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.

公开(公告)号：US20220108923A1

公开(公告)日：2022-04-07

申请号：US17553950

申请日：2021-12-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Veeraraghavan Basker ,  Alexander Reznicek ,  Junli Wang

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.

公开(公告)号：US20210134671A1

公开(公告)日：2021-05-06

申请号：US16669231

申请日：2019-10-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Veeraraghavan Basker ,  Alexander Reznicek ,  Junli Wang

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.

公开(公告)号：US10943990B2

公开(公告)日：2021-03-09

申请号：US16171081

申请日：2018-10-25

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Victor W. C. Chan ,  Gangadhara Raja Muthinti ,  Veeraraghavan Basker ,  Junli Wang ,  Kisik Choi ,  Su Chen Fan

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/417

Abstract: Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.

公开(公告)号：US10586739B2

公开(公告)日：2020-03-10

申请号：US15795370

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Theodorus Standaert ,  Junli Wang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/762

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

公开(公告)号：US09379025B1

公开(公告)日：2016-06-28

申请号：US14744080

申请日：2015-06-19

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/283 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/02304 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76897 ,  H01L21/823418 ,  H01L27/0924

Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. After forming replacement metal gate (RMG) FinFETs on a surface layer of a silicon on insulator (SOI) wafer, and growing unmerged epitaxially (epi) on the fins, the epi is capped with dielectric and an inter-level dielectric (ILD) layer is formed on the SOI wafer. The said ILD layer is patterned to an upper surface of the epi above encased fins in a timed etch. Then, etching, preferably with an etchant selective to silicon, the epi is opened to, and into, the fins. The resulting orifices are filled with conductive material to form source drain contacts.

Abstract translation: 一种形成场效应晶体管（FET）的方法，以及形成包括FET的集成电路（IC）芯片。 在绝缘体上硅（SOI）晶片的表面层上形成替代金属栅极（RMG）FinFET并在散热片上外延生长（epi）后，epi被电介质和层间电介质层（ILD）层 形成在SOI晶片上。 所述ILD层在定时蚀刻中被图案化到包围的鳍片上面的epi的上表面。 然后，优选用对硅选择性的蚀刻剂进行蚀刻，将epi打开并进入翅片。 所得到的孔用导电材料填充以形成源极漏极接触。