公开(公告)号：US20230053981A1

公开(公告)日：2023-02-23

申请号：US17406186

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brian D. Barrick ,  Dung Q. Nguyen ,  Richard J. Eickemeyer ,  John B. Griswell, JR. ,  Balaram Sinharoy ,  Brian W. Thompto ,  Tu-An T. Nguyen

IPC: G06F9/30 ,  G06F9/38

Abstract: Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

公开(公告)号：US20220413868A1

公开(公告)日：2022-12-29

申请号：US17358183

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Brian D. Barrick ,  Dung Q. Nguyen ,  Brian W. Thompto ,  Tu-An T. Nguyen ,  Salma Ayub

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments for fast perfect issue of dependent instructions in a distributed issue queue system. Producer information of a producer instruction is inserted in a lookup entry in a lookup table, the lookup entry being allocated to a register. It is determined that the register corresponding to the lookup entry is a source for a dependent instruction. Responsive to storing the dependent instruction in an issue queue, the producer information is stored in a back-to-back entry of a back-to-back wakeup table, the back-to-back entry corresponding to the dependent instruction. The producer instruction is issued which causes the producer information of the producer instruction to be sent to the back-to-back wakeup table. It is determined that there is a match between the producer information and the back-to-back entry for the dependent instruction, and the dependent instruction is caused to issue based on the match.

公开(公告)号：US20190384611A1

公开(公告)日：2019-12-19

申请号：US16008583

申请日：2018-06-14

Applicant: International Business Machines Corporation

Inventor： Michael J. Genden ,  Eula Faye Abalos Tolentino ,  Dung Q. Nguyen ,  Jeffrey C. Brownscheidle ,  Tu-An T. Nguyen ,  David S. Walder

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions. A branch execution unit is provided as part of the instruction fetch unit to execute the selected conditional branch instruction, followed by dynamically updated any related non-executed instructions in the BRQ.

公开(公告)号：US10120693B2

公开(公告)日：2018-11-06

申请号：US15939367

申请日：2018-03-29

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Jeffrey C. Brownscheidle ,  Sundeep Chadha ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Salim A. Shah ,  Brian W. Thompto

IPC: G06F9/38

Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

公开(公告)号：US20170293489A1

公开(公告)日：2017-10-12

申请号：US15093192

申请日：2016-04-07

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Jeffrey C. Brownscheidle ,  Sundeep Chadha ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Salim A. Shah ,  Brian W. Thompto

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/3887

Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

公开(公告)号：US12050538B2

公开(公告)日：2024-07-30

申请号：US17708785

申请日：2022-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert J. Sonnelitter, III ,  Ekaterina M. Ambroladze ,  Timothy Bronson ,  Michael A. Blake ,  Tu-An T. Nguyen

IPC: G06F12/0891 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0817

CPC classification number: G06F12/0891 ,  G06F9/3816 ,  G06F12/0811 ,  G06F12/0824

Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

公开(公告)号：US11853212B2

公开(公告)日：2023-12-26

申请号：US17713267

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Vesselina Papazova

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

公开(公告)号：US20230315638A1

公开(公告)日：2023-10-05

申请号：US17713264

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Winston Herring ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084 ,  G06F12/0815 ,  G06F12/0897 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F9/34 ,  G06F9/3816 ,  G06F12/0897

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

公开(公告)号：US20230315636A1

公开(公告)日：2023-10-05

申请号：US17657169

申请日：2022-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D. Kohl ,  Winston Herring ,  Tu-An T. Nguyen ,  Gregory William Alexander ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084

CPC classification number: G06F12/084

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

公开(公告)号：US10776122B2

公开(公告)日：2020-09-15

申请号：US16008583

申请日：2018-06-14

Applicant: International Business Machines Corporation

Inventor： Michael J. Genden ,  Eula Faye Abalos Tolentino ,  Dung Q. Nguyen ,  Jeffrey C. Brownscheidle ,  Tu-An T. Nguyen ,  David S. Walder

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30

Abstract: Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions. A branch execution unit is provided as part of the instruction fetch unit to execute the selected conditional branch instruction, followed by dynamically updated any related non-executed instructions in the BRQ.