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公开(公告)号：US12118329B2
公开(公告)日：2024-10-15
申请号：US16744824
申请日：2020-01-16
发明人： Mingu Kang , Seyoung Kim , Kyu-Hyoun Kim
CPC分类号： G06F7/523 , G06N3/065 , G11C27/026 , G06N3/02
摘要： Mixed signal multipliers and methods for operating the same include a sampling capacitor and an accumulate capacitor. A sampling switch is configured to store an analog value on the sampling capacitor when a digital bit value of a digital signal is one and to store a zero when the digital bit value of the digital signal is a zero. An accumulate switch is configured to store an average of the stored value of the sampling capacitor and a previous stored value of the accumulate capacitor. A processor is configured to alternately trigger the sampling capacitor and the sampling capacitor for each bit value in the digital signal.
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公开(公告)号：US11455142B2
公开(公告)日：2022-09-27
申请号：US16432358
申请日：2019-06-05
发明人： Ankur Agrawal , Silvia Mueller , Kailash Gopalakrishnan , Bruce Fleischer , Balaram Sinharoy , Mingu Kang
IPC分类号： G06F7/544
摘要： Embodiments for implementing a fused multiply-multiply-accumulate (“FMMA”) unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.
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13.发明申请公开(公告)号：US20220300797A1
公开(公告)日：2022-09-22
申请号：US17203705
申请日：2021-03-16
发明人： Seyoung Kim , Eun Kyung Lee , Mingu Kang , Seonghoon Woo
IPC分类号： G06N3/063 , G06N3/04 , G06N3/08 , G11C11/4063
摘要： An electronic circuit includes word lines; bit lines intersecting the word lines at a plurality of grid points; and resistive processing units located at the grid points. Baseline stochastic pulse input units are coupled to the word lines; differential stochastic pulse input units are coupled to the word lines; and bitline stochastic pulse input units are coupled to the bit lines. Control circuitry coupled to the pulse input units is configured to cause each of the baseline stochastic pulse input units to generate a baseline pulse train using base input data, each of the differential stochastic pulse input units to generate a differential pulse train using differential input data defining differences from the base input data, and each of the bitline stochastic pulse input units to generate a bitline pulse train using bit line input data. Neural network weights can thus be stored in the resistive processing units.
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公开(公告)号：US20210318852A1
公开(公告)日：2021-10-14
申请号：US16847505
申请日：2020-04-13
发明人： Seyoung Kim , Mingu Kang , Kyu-hyoun Kim , Seonghoon Woo
摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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公开(公告)号：US20210279560A1
公开(公告)日：2021-09-09
申请号：US16808708
申请日：2020-03-04
发明人： Mingu Kang , Seyoung Kim , Seonghoon Woo
摘要： A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.
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16.发明申请公开(公告)号：US20210208847A1
公开(公告)日：2021-07-08
申请号：US16737440
申请日：2020-01-08
发明人： Mingu Kang , Seyoung Kim , Kyu-hyoun Kim , Eun Kyung Lee
摘要： A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.
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公开(公告)号：US12112242B2
公开(公告)日：2024-10-08
申请号：US16986506
申请日：2020-08-06
发明人： Mingu Kang , Seonghoon Woo , Eun Kyung Lee , Sukjay Chey
摘要： Techniques for performing improved machine learning using decision trees are disclosed. In one example, a system includes a plurality of decision tree structures, and configuration logic operatively coupled to the plurality of decision tree structures. The configuration logic selectively configures the plurality of decision tree structures to form at least one of: one or more combined decision tree structures, wherein a combined decision tree structure comprises multiple interconnected ones of the plurality of decision tree structures; and one or more individual decision tree structures, wherein an individual decision tree structure comprises a single one of the plurality of decision tree structures.
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公开(公告)号：US11793002B2
公开(公告)日：2023-10-17
申请号：US17308499
申请日：2021-05-05
发明人： Seonghoon Woo , Seyoung Kim , Mingu Kang
CPC分类号： H10B63/30 , G11C11/1673 , G11C11/1675 , H10N50/10 , H10N50/85
摘要： A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.
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公开(公告)号：US20230188146A1
公开(公告)日：2023-06-15
申请号：US17550493
申请日：2021-12-14
发明人： Kyu-hyoun Kim , Mingu Kang , Ankur Agrawal , Monodeep Kar
IPC分类号： H03M1/00
CPC分类号： H03M1/002
摘要： An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
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公开(公告)号：US20230058641A1
公开(公告)日：2023-02-23
申请号：US17406704
申请日：2021-08-19
发明人： Monodeep Kar , Ankur Agrawal , Mingu Kang , Kyu-hyoun Kim
摘要： Techniques for performing analog-to-digital conversion are disclosed. For example, a method performs an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.
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