公开(公告)号：US11347517B2

公开(公告)日：2022-05-31

申请号：US16447588

申请日：2019-06-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kailash Gopalakrishnan ,  Sunil Shukla ,  Jungwook Choi ,  Silvia Mueller ,  Bruce Fleischer ,  Vijayalakshmi Srinivasan ,  Ankur Agrawal ,  Jinwook Oh

IPC分类号： G06F9/38 ,  G06F15/80

摘要： A reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture includes reduced precision execution units with a majority of the execution units operating at reduced precision and a minority of the execution units are capable of operating at higher precision. The execution units operate in parallel within a programmable execution element to share instruction fetch, decode, and issue pipelines and operate on the same instruction in lock-step to minimize instruction-related overhead.

公开(公告)号：US11216281B2

公开(公告)日：2022-01-04

申请号：US16412072

申请日：2019-05-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Bruce Fleischer ,  Kailash Gopalakrishnan ,  Jinwook Oh ,  Sunil Shukla ,  Silvia Mueller

IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F9/30

摘要： Various embodiments are provided for facilitating data processing by one or more processors in a computing system. An instruction to be executed may be obtained. The instruction is a single instruction multiple data (SIMD) reduction operation of an operand vector with a plurality of vector elements. The SIMD reduction operation may be executed to produce a result vector with a plurality of alternative vector elements. One or more reduction functions may be performed on each of a pair of vector elements from the plurality of vector elements of the operand vector and a result of the one or more reduction functions may be placed in a corresponding vector element of the result vector.

公开(公告)号：US11455142B2

公开(公告)日：2022-09-27

申请号：US16432358

申请日：2019-06-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ankur Agrawal ,  Silvia Mueller ,  Kailash Gopalakrishnan ,  Bruce Fleischer ,  Balaram Sinharoy ,  Mingu Kang

IPC分类号： G06F7/544

摘要： Embodiments for implementing a fused multiply-multiply-accumulate (“FMMA”) unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.