公开(公告)号：US11004868B2

公开(公告)日：2021-05-11

申请号：US16487417

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Uygar E. Avci ,  Joshua M. Howard ,  Ian A. Young ,  Daniel H. Morris

IPC: H01L29/78 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11592 ,  H01L29/51

Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

公开(公告)号：US10998495B2

公开(公告)日：2021-05-04

申请号：US16329721

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/10 ,  H01L41/187 ,  H01L41/193 ,  H01L41/20 ,  G11C11/16 ,  H01L41/00 ,  H01L27/22 ,  H01L43/08 ,  H01F10/32 ,  H01L43/02 ,  H01F10/12

Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.

公开(公告)号：US10957844B2

公开(公告)日：2021-03-23

申请号：US16346872

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jasmeet S. Chawla ,  Sasikanth Manipatruni ,  Robert L. Bristol ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00 ,  H03K19/18

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：US10901486B2

公开(公告)日：2021-01-26

申请号：US16384715

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young ,  Tanay Karnik ,  Huichu Liu

IPC: G06F1/3234 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  H03K19/0185

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20200372333A1

公开(公告)日：2020-11-26

申请号：US16989371

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Hai Li ,  Ian A. Young

IPC: G06N3/063 ,  H03K3/03

Abstract: Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.

公开(公告)号：US20200286687A1

公开(公告)日：2020-09-10

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L27/108 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US10720504B2

公开(公告)日：2020-07-21

申请号：US15751104

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/66

Abstract: Described is an apparatus which comprises a transistor including: a layer of ferroelectric material; a layer of insulating material; and an oxide layer or a metal layer sandwiched between the layer of ferroelectric material and the layer of insulating material, wherein thickness of the ferroelectric material is less than thickness of the layer of insulating material; and a driver coupled to the transistor. Described is an apparatus which comprises: a transistor including: a first oxide layer of High-K material; a second oxide layer; and a layer of nanocrystals sandwiched between the first and second oxide layers, wherein thickness of first oxide layer is greater than thickness of the second oxide layer; and a driver coupled to the transistor.

公开(公告)号：US10707846B2

公开(公告)日：2020-07-07

申请号：US15992080

申请日：2018-05-29

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H03K3/356 ,  H03K3/3562 ,  H01L29/66 ,  H03K3/012

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.

公开(公告)号：US20200211608A1

公开(公告)日：2020-07-02

申请号：US16349575

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14 ,  H03K19/18 ,  H03K19/185

Abstract: An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

公开(公告)号：US10651182B2

公开(公告)日：2020-05-12

申请号：US16146663

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11514 ,  H01L27/11504 ,  H03K19/20 ,  G11C5/06 ,  G11C11/22 ,  H01L29/51

Abstract: An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.