公开(公告)号：US09804842B2

公开(公告)日：2017-10-31

申请号：US14581535

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Jesus Corbal San Adrian ,  Dennis R. Bradford ,  Benjamin C. Chaffin ,  Taraneh Bahrami ,  Jonathan C. Hall ,  Thomas B. Maciukenas ,  Roger Gramunt ,  Rohan Sharma

IPC: G06F9/302 ,  G06F9/305 ,  G06F9/312 ,  G06F9/315 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/30101 ,  G06F15/8084

Abstract: An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask register to be logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated; a control register to store an unusable portion of the mask value; architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.

公开(公告)号：US20160179515A1

公开(公告)日：2016-06-23

申请号：US14581815

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Jesus Corbal San Adrian ,  Robert N. Hanek ,  Warren E. Ferguson ,  Taraneh Bahrami ,  Avi A. Tevet ,  Dennis R. Bradford ,  Michael Ferry ,  Jingwei Zhang

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3861 ,  G06F9/4552 ,  G06F9/45525

Abstract: An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

Abstract translation: 一种用于对数学指令的输入进行检查并选择有效地管理处理器的架构状态的默认序列的装置和方法。 例如，处理器的一个实施例包括：使用一个或多个源操作数执行多个数学运算的算术逻辑单元（ALU）; 指令检查逻辑以评估当前数学指令的源操作数，并且基于评估来确定是否执行默认操作序列，包括由ALU执行当前数学指令或跳转到适于 为具有比默认操作序列更有效的特定类型的源操作数的数学指令提供结果。

公开(公告)号：US20150220345A1

公开(公告)日：2015-08-06

申请号：US13997791

申请日：2012-12-19

Applicant: INTEL CORPORATION

Inventor： Jesus Corbal ,  Dennis R. Bradford ,  Jonathan C. Hall ,  Thomas D. Fletcher ,  Brian J. Hickmann ,  Dror Markovich ,  Amit Gradstein

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/3001 ,  G06F9/30036 ,  Y02D10/152 ,  Y02D10/24

Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

Abstract translation: 处理器包括指令调度和调度（调度/调度）单元，以接收单个指令多数据（SIMD）指令，以对存储在由第一源操作数指示的存储位置中的多个数据元素执行操作。 指令调度/调度单元是基于第二源操作数来确定将不被操作以生成写入目的地操作数的结果的第一数据元素。 处理器还包括耦合到指令调度/调度单元的多个处理单元，以矢量方式处理SIMD指令的数据单元，以及耦合到指令调度/调度单元的功率管理单元，以减少第一 所述处理元件被配置为处理所述第一数据元素。

公开(公告)号：US11740904B2

公开(公告)日：2023-08-29

申请号：US17524624

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

IPC: G06F9/30 ,  G06F9/34 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696 ,  G06F9/30018 ,  H01L29/66

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US11693691B2

公开(公告)日：2023-07-04

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/383

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11093277B2

公开(公告)日：2021-08-17

申请号：US16913265

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US10719320B2

公开(公告)日：2020-07-21

申请号：US15665212

申请日：2017-07-31

Applicant: INTEL CORPORATION

Inventor： Federico Ardanaz ,  Roger Gramunt ,  Jesus Corbal ,  Dennis R. Bradford ,  Jonathan M. Eastep

IPC: G06F1/32 ,  G06F9/30 ,  G05F1/10 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3206 ,  G06F1/30 ,  G06F1/26

Abstract: An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.

公开(公告)号：US10268539B2

公开(公告)日：2019-04-23

申请号：US14981649

申请日：2015-12-28

Applicant: Intel Corporation

Inventor： Wei Wu ,  Brian J. Hickmann ,  Dennis R. Bradford

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00 ,  H03M13/13 ,  H03M13/15 ,  H03M13/27

Abstract: An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.

公开(公告)号：US09785436B2

公开(公告)日：2017-10-10

申请号：US13631071

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/35 ,  G06F9/345 ,  G06F9/355

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/355

Abstract: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

公开(公告)号：US12135981B2

公开(公告)日：2024-11-05

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.