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公开(公告)号：US11061463B2
公开(公告)日：2021-07-13
申请号：US15689646
申请日：2017-08-29
申请人： INTEL CORPORATION
IPC分类号： G06F1/32 , G06F1/3234 , G06F1/3287 , G06F1/3293
摘要： Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.
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公开(公告)号：US10261904B2
公开(公告)日：2019-04-16
申请号：US15835384
申请日：2017-12-07
申请人： Intel Corporation
发明人： Chunhui Zhang , George Z. Chrysos , Edward T. Grochowski , Ramacharan Sundararaman , Chung-Lun Chan , Federico Ardanaz
IPC分类号： G06F9/38 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/0831 , G06F12/0842
摘要： Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.
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公开(公告)号：US20190034203A1
公开(公告)日：2019-01-31
申请号：US15665212
申请日：2017-07-31
申请人： INTEL CORPORATION
摘要： An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.
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公开(公告)号：US20170255247A1
公开(公告)日：2017-09-07
申请号：US15060326
申请日：2016-03-03
申请人： Intel Corporation
发明人： Federico Ardanaz , Jonathan Eastep , Richard Greco
CPC分类号： G06F1/3237 , G06F1/26 , G06F1/266 , G06F1/28 , G06F1/3206 , G06F1/3287
摘要： Apparatus and methods may provide for a central power control unit to grant a power allowance to each of a plurality of computer components and to allocate a shared power pool locally accessible to each of the plurality of computer components when one or more of the plurality of components needs to exceed its granted power allowance.
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公开(公告)号：US11650652B2
公开(公告)日：2023-05-16
申请号：US17357479
申请日：2021-06-24
申请人： INTEL CORPORATION
IPC分类号： G06F1/32 , G06F1/3234 , G06F1/3287 , G06F1/3293
CPC分类号： G06F1/325 , G06F1/3287 , G06F1/3293 , Y02D10/00
摘要： Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.
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公开(公告)号：US20200310515A1
公开(公告)日：2020-10-01
申请号：US16369580
申请日：2019-03-29
申请人： Intel Corporation
IPC分类号： G06F1/3206 , G06F1/3234
摘要： Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.
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公开(公告)号：US10146287B2
公开(公告)日：2018-12-04
申请号：US15088531
申请日：2016-04-01
申请人： Intel Corporation
发明人： Federico Ardanaz , Ian M. Steiner , Jonathan M. Eastep , Richard J. Greco , Krishnakanth V. Sistla , Micah Barany , Andrew J. Herdrich
摘要： Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.
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公开(公告)号：US09753526B2
公开(公告)日：2017-09-05
申请号：US14581854
申请日：2014-12-23
申请人： Intel Corporation
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/3287 , G06F1/3293 , Y02D10/122 , Y02D10/171
摘要： Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.
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公开(公告)号：US11061460B2
公开(公告)日：2021-07-13
申请号：US16457354
申请日：2019-06-28
申请人： Intel Corporation
IPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3296
摘要： Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.
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公开(公告)号：US10719320B2
公开(公告)日：2020-07-21
申请号：US15665212
申请日：2017-07-31
申请人： INTEL CORPORATION
IPC分类号： G06F1/32 , G06F9/30 , G05F1/10 , G06F1/3234 , G06F9/38 , G06F1/3206 , G06F1/30 , G06F1/26
摘要： An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.
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