公开(公告)号：US20190235849A1

公开(公告)日：2019-08-01

申请号：US16378641

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： Paul Caprioli ,  Jeffrey J. Cook

IPC: G06F8/52 ,  G06F12/02 ,  G06F9/455

CPC classification number: G06F8/52 ,  G06F9/30 ,  G06F9/45525 ,  G06F11/3409 ,  G06F12/023

Abstract: Technologies for optimized binary translation include a computing device that determines a cost-benefit metric associated with each translated code block of a translation cache. The cost-benefit metric is indicative of translation cost and performance benefit associated with the translated code block. The translation cost may be determined by measuring translation time of the translated code block. The cost-benefit metric may be calculated using a weighted cost-benefit function based on an expected workload of the computing device. In response to determining to free space in the translation cache, the computing device determines whether to discard each translated code block as a function of the cost-benefit metric. In response to determining to free space in the translation cache, the computing device may increment an iteration count and skip each translated code block if the iteration count modulo the corresponding cost-benefit metric is non-zero. Other embodiments are described and claimed.

公开(公告)号：US09946538B2

公开(公告)日：2018-04-17

申请号：US14710372

申请日：2015-05-12

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Karthikeyan Avudaiyappan

IPC: G06F9/30 ,  G06F9/455

CPC classification number: G06F9/30 ,  G06F9/3017 ,  G06F9/45525

Abstract: A method and apparatus for providing support for self modifying guest code. The apparatus includes a memory, a hardware buffer, and a processor. The processor is configured to convert guest code to native code and store converted native code equivalent of the guest code into a code cache portion of the processor. The processor is further configured to maintain the hardware buffer configured for tracking respective locations of converted code in a code cache. The hardware buffer is updated based a respective access to a respective location in the memory associated with a respective location of converted code in the code cache. The processor is further configured to perform a request to modify a memory location after accessing the hardware buffer.

公开(公告)号：US09842428B2

公开(公告)日：2017-12-12

申请号：US14679720

申请日：2015-04-06

Applicant: SAMSUNG ELECTRONICS COMPANY, LTD.

Inventor： Zhenghong Wang

IPC: G09G5/00 ,  G06T15/80 ,  G06T15/00 ,  G06F9/455

CPC classification number: G06T15/80 ,  G06F9/45525 ,  G06T15/005

Abstract: A method for dynamically configuring a graphics pipeline system. The method includes determining an optimal pipeline based on: estimating one or more of memory power consumption and computation power consumption of storing and regenerating intermediate results based on graphics state information and one or more factors; determining granularity for the optimal graphics pipeline configuration based on the graphics state information and the one or more factors; collecting runtime information for primitives from graphics pipeline hardware including factors from tessellation or using graphics state information for determining geometry expansion at an output of one or more shader stages; and determining intermediate results to save from a previous processing pass by comparing memory power consumption needed to save the intermediate results with computation power as well as memory power needed for regenerating the intermediate results in one or more later tile rendering passes.

公开(公告)号：US09733909B2

公开(公告)日：2017-08-15

申请号：US14807308

申请日：2015-07-23

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/45 ,  G06F9/44 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F8/443 ,  G06F8/70 ,  G06F9/45525 ,  G06F9/5083

Abstract: A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a converter wherein a system emulation/virtualization converter and an application code converter implement a system emulation process, and wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the system converter or the system emulator. The system further includes a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address, wherein a load will check for a same address of subsequent loads from a same thread, and a thread checking process that enable other thread store checks against the entire load queue and a monitor extension.

公开(公告)号：US09696992B2

公开(公告)日：2017-07-04

申请号：US14581815

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Jesus Corbal San Adrian ,  Robert N. Hanek ,  Warren E. Ferguson ,  Taraneh Bahrami ,  Avi A. Tevet ,  Dennis R. Bradford ,  Michael Ferry ,  Jingwei Zhang

IPC: G06F7/38 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3861 ,  G06F9/4552 ,  G06F9/45525

Abstract: An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

公开(公告)号：US20170003938A1

公开(公告)日：2017-01-05

申请号：US14755703

申请日：2015-06-30

Applicant: Citrix Systems, Inc.

Inventor： Dan Gulkis

IPC: G06F9/44 ,  G06F9/445

CPC classification number: G06F8/315 ,  G06F9/445 ,  G06F9/44521 ,  G06F9/45504 ,  G06F9/45525

Abstract: Methods, systems, and computer-readable media for providing a virtualization layer for mobile applications are presented. A computing device may parse code of an application to identify a first set of one or more classes in the application. The computing device may transmit code usable by the first set of one or more classes to a module accessible to the application and create a second set of one or more classes in the application to replace the first set of one or more classes, wherein the second set of one or more classes does not inherit from the first set of one or more classes in an object hierarchy. In some embodiments, the second set of one or more classes provides at least one different function from the first set of one or more classes. The computing device may execute the application comprising the second set of one or more classes.

Abstract translation: 提出了用于为移动应用提供虚拟化层的方法，系统和计算机可读介质。 计算设备可以解析应用的代码以识别应用中的一个或多个类的第一组。 计算设备可以将由第一组一个或多个类别可用的代码传送到应用程序可访问的模块，并在应用程序中创建一个或多个类别的第二组来替换第一组一个或多个类别，其中第二组 一个或多个类的集合不会从对象层次结构中的第一组一个或多个类继承。 在一些实施例中，一个或多个类的第二组从一个或多个类的第一组提供至少一个不同的功能。 计算设备可以执行包括第二组一个或多个类的应用。

公开(公告)号：US09529628B2

公开(公告)日：2016-12-27

申请号：US14222260

申请日：2014-03-21

Applicant: VMware, Inc.

Inventor： Lan Vu ,  Hari Sivaraman ,  Rishi Bidarkar

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/44

CPC classification number: G06F9/45525 ,  G06F9/4484 ,  G06F9/50

Abstract: Systems and techniques are described for modifying an executable file of an application and executing the application using the modified executable file. A described technique includes receiving, by a virtual machine, a request to perform an initial function of an application and an executable file for the application. The virtual machine modifies the executable file by redirecting the executable file to a custom runtime library that includes a custom function configured to initialize the application and to place the application in a paused state. A custom function call is added to the custom function in the executable file. The virtual machine initializes the application by executing the modified executable file, the executing causing the custom function to initialize the application and place the application in a paused state.

Abstract translation: 描述了用于修改应用程序的可执行文件并使用修改的可执行文件执行应用程序的系统和技术。 所描述的技术包括由虚拟机接收执行应用的初始功能的请求和用于该应用的可执行文件。 虚拟机通过将可执行文件重定向到自定义运行时库来修改可执行文件，该库包括配置为初始化应用程序并将应用程序置于暂停状态的自定义功能。 自定义函数调用将添加到可执行文件中的自定义函数中。 虚拟机通过执行修改的可执行文件来初始化应用程序，执行导致自定义函数初始化应用程序并将应用程序置于暂停状态。

公开(公告)号：US09483275B2

公开(公告)日：2016-11-01

申请号：US13976046

申请日：2011-12-16

Applicant: Arvind Krishnaswamy ,  Daniel M Lavery

Inventor： Arvind Krishnaswamy ,  Daniel M Lavery

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46

CPC classification number: G06F9/3861 ,  G06F8/49 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/45525 ,  G06F9/467

Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.

Abstract translation: 方法和系统在支持事务的系统中使用异常代码专门化。 该方法和系统包括将一个或多个无分支指令插入到计算机指令序列中。 无分支指令包括一个或多个可执行的指令，如果共同发生的条件被满足并且包括一个或多个指令，其被配置为在不满足共同发生的条件时引发异常。

公开(公告)号：US20160306641A1

公开(公告)日：2016-10-20

申请号：US14686893

申请日：2015-04-15

Applicant: International Business Machines Corporation

Inventor： Roee Hay ,  Omer Tripp

IPC: G06F9/455 ,  G06F9/44

CPC classification number: G06F11/3608 ,  G06F8/434 ,  G06F8/75 ,  G06F9/45525 ,  G06F11/36 ,  G06F11/3604 ,  G06F11/3672

Abstract: A method includes receiving a program code at a processor. The method also includes generating, via the processor, a heap model corresponding to the program code. The method further includes detecting, via the processor, a linearizable data structure in the program code. The method also further includes modifying, via the processor, the heap model based on the detected linearizable data structure. The method also further includes analyzing, via the processor, the program code using the modified heap model.

Abstract translation: 一种方法包括在处理器处接收程序代码。 该方法还包括经由处理器产生与程序代码相对应的堆模型。 该方法还包括经由处理器检测程序代码中的可线性化数据结构。 该方法还包括基于检测到的线性化数据结构，经由处理器修改堆模型。 该方法还包括经由处理器使用修改的堆模型来分析程序代码。

公开(公告)号：US09430199B2

公开(公告)日：2016-08-30

申请号：US13398793

申请日：2012-02-16

Applicant: Andy Glaister ,  Blaise Pascal Tine ,  Derek Sessions ,  Mikhail Lyapunov ,  Yuri Dotsenko

Inventor： Andy Glaister ,  Blaise Pascal Tine ,  Derek Sessions ,  Mikhail Lyapunov ,  Yuri Dotsenko

IPC: G06F9/45 ,  G06T15/00 ,  G06F9/455

CPC classification number: G06F8/433 ,  G06F8/452 ,  G06F9/45525 ,  G06T15/005

Abstract: Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.

Abstract translation: 这里描述了线程循环中间表示（IR）代码的优化。 一个实施例涉及一种算法，其基于数据流分析，计算在线程循环开始时加载并在从线程循环退出时存储的临时变量集合。 另一个实施例涉及减少线程循环跳闸的大小，用于通常发现的情况，其中一条计算着色器由单个线程（或可编程序分析的线程范围）执行。 在另一个实施例中，计算着色器线索索引被缓存以避免过分的划分，进一步提高执行速度。