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公开(公告)号：US20140201504A1
公开(公告)日：2014-07-17
申请号：US14216884
申请日：2014-03-17
Applicant: INTEL CORPORATION
Inventor： Alex Pineiro , Thomas D. Fletcher , Brian J. Hickmann
IPC: G06F9/30
CPC classification number: G06F9/3001 , G06F1/035 , G06F9/3895 , G06F2101/08 , G06F2101/10 , G06F2101/12
Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.
Abstract translation: 描述了具有可执行第一指令并执行第二指令的功能单元的半导体芯片。 第一条指令是将两个操作数相乘的指令。 第二条指令是根据C0 + C1X2 + C2X22近似函数的指令。 功能单元具有乘法电路。 所述乘法器电路具有：i）第一输入，用于接收所述第一指令的第一操作数的比特并接收所述第二指令的C1项的比特; ii）用于接收第一指令的第二操作数的比特并接收第二指令的X2项的比特的第二输入。
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公开(公告)号：US11520562B2
公开(公告)日：2022-12-06
申请号：US16557959
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin
Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.
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公开(公告)号：US11003455B2
公开(公告)日：2021-05-11
申请号：US16398183
申请日：2019-04-29
Applicant: Intel Corporation
Inventor： Andrew T. Forsyth , Brian J. Hickmann , Jonathan C. Hall , Christopher J. Hughes
IPC: G06F9/38 , G06F9/30 , G06F12/0875 , G06F12/1027 , G06F15/80 , G06F13/42
Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
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公开(公告)号：US20190384575A1
公开(公告)日：2019-12-19
申请号：US16557959
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin
Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.
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公开(公告)号：US10133577B2
公开(公告)日：2018-11-20
申请号：US13997791
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Jesus Corbal , Dennis R. Bradford , Jonathan C. Hall , Thomas D. Fletcher , Brian J. Hickmann , Dror Markovich , Amit Gradstein
Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.
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Patent Agency Ranking
公开(公告)号：US20170185476A1
公开(公告)日：2017-06-29
申请号：US14981649
申请日：2015-12-28
Applicant: Intel Corporation
Inventor： Wei Wu , Brian J. Hickmann , Dennis R. Bradford
CPC classification number: G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/13 , H03M13/15 , H03M13/1575 , H03M13/27 , H03M13/616
Abstract: An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.
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公开(公告)号：US09645826B2
公开(公告)日：2017-05-09
申请号：US14975292
申请日：2015-12-18
Applicant: Intel Corporation
Inventor： Andrew T. Forsyth , Brian J. Hickmann , Jonathan C. Hall , Christopher J. Hughes
IPC: G06F12/10 , G06F9/38 , G06F9/30 , G06F12/0875 , G06F12/1027 , G06F15/80 , G06F13/42
CPC classification number: G06F9/3853 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F9/30105 , G06F9/30145 , G06F9/3804 , G06F9/3824 , G06F9/3836 , G06F9/3887 , G06F12/0875 , G06F12/1027 , G06F13/4282 , G06F15/8007 , G06F2212/1016 , G06F2212/452 , G06F2212/68
Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
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18.发明授权Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values 有权根据输入数据值降低融合乘法（FMA）单元中的功耗公开(公告)号：US09152382B2
公开(公告)日：2015-10-06
申请号：US13664689
申请日：2012-10-31
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Dennis R. Bradford , Thomas D. Fletcher
CPC classification number: G06F7/60 , G06F1/324 , G06F1/3243 , G06F7/48 , G06F7/483 , G06F7/5443 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F2207/3884 , Y02D10/126 , Y02D10/152
Abstract: In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，融合乘法（FMA）电路被配置为接收多个输入数据值以对输入数据值执行FMA指令。 电路包括耦合到乘法器单元的输出的乘法器单元和加法器单元，以及用于接收输入数据值并降低开关活动并因此降低电路的一个或多个组件的功耗的控制逻辑，其基于 一个或多个输入数据值的值。 描述和要求保护其他实施例。
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公开(公告)号：US11169776B2
公开(公告)日：2021-11-09
申请号：US16457318
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin , Brian J. Hickmann , Valentina Popescu
Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
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公开(公告)号：US20190324723A1
公开(公告)日：2019-10-24
申请号：US16457318
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin , Brian J. Hickmann , Valentina Popescu
Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
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