-
公开(公告)号：US11520562B2
公开(公告)日：2022-12-06
申请号：US16557959
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin
Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.
-
公开(公告)号：US20190384575A1
公开(公告)日：2019-12-19
申请号：US16557959
申请日：2019-08-30
Applicant: Intel Corporation
Inventor： Brian J. Hickmann , Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin
Abstract: A method comprising storing a plurality of entries, each entry of the plurality of entries associated with a portion of a range of input values, each entry of the plurality of entries comprising a set of coefficients defining a power series approximation; selecting first entry of the plurality of entries based on a determination that a floating point input value is within a portion of the range of input values that is associated with the first entry; and calculating an output value by evaluating the power series approximation defined by the set of coefficients of the first entry at the floating point input value.
-
公开(公告)号：US11169776B2
公开(公告)日：2021-11-09
申请号：US16457318
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin , Brian J. Hickmann , Valentina Popescu
Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
-
公开(公告)号：US20190324723A1
公开(公告)日：2019-10-24
申请号：US16457318
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Nitin N. Garegrat , Maciej Urbanski , Michael Rotzin , Brian J. Hickmann , Valentina Popescu
Abstract: Systems, apparatuses and methods may provide for technology that in response to an identification that one or more hardware units are to execute on a first type of data format, decomposes a first original floating point number to a plurality of first segmented floating point numbers that are to be equivalent to the first original floating point number. The technology may further in response to the identification, decompose a second original floating point number to a plurality of second segmented floating point numbers that are to be equivalent to the second original floating point number. The technology may further execute a multiplication operation on the first and second segmented floating point numbers to multiply the first segmented floating point numbers with the second segmented floating point numbers.
-
-
-
Search Results
4
records
(took 0.017 seconds)
