公开(公告)号：US06274397B1

公开(公告)日：2001-08-14

申请号：US09323351

申请日：1999-06-01

Applicant: Wen-Cheng Chien ,  Ho-Yin Yiu ,  Hui-Chen Chu

Inventor： Wen-Cheng Chien ,  Ho-Yin Yiu ,  Hui-Chen Chu

IPC: H01L2166

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L22/20 ,  H01L2924/014

Abstract: A method for eliminating metal line corrosion for semiconductor packages where exposed metal lines are exposed to the atmosphere for an extended period of time. A passivation layer is deposited over the active die of the semiconductor package, a layer of polymer film is deposited over the passivation layer and over the exposed conducting lines. At the time that the semiconductor package must be tested, including testing for corrosion of the exposed metal lines, the polymer layer is removed and the molding compound is applied. The semiconductor package is now tested. The added step of depositing a layer of polymer film has protected the interconnecting conducting lines from corrosion.

Abstract translation: 一种用于消除暴露的金属线路暴露于大气中延长的时间段的半导体封装的金属线腐蚀的方法。 钝化层沉积在半导体封装的有源裸片上，聚合物膜层沉积在钝化层上并暴露在导电线上。 在半导体封装必须被测试的时候，包括暴露的金属线的腐蚀测试，去除聚合物层并施加模塑料。 该半导体封装已经过测试。 沉积聚合物膜层的添加步骤保护互连导线免受腐蚀。

公开(公告)号：US09088206B2

公开(公告)日：2015-07-21

申请号：US13359466

申请日：2012-01-26

Applicant: Ho-Yin Yiu ,  Chien-Hung Liu ,  Wei-Chung Yang ,  Bai-Yao Lou

Inventor： Ho-Yin Yiu ,  Chien-Hung Liu ,  Wei-Chung Yang ,  Bai-Yao Lou

IPC: H01L29/06 ,  H01L27/06 ,  H04B1/02 ,  H02M3/155 ,  H02M3/00 ,  H01F17/00 ,  H01L23/64 ,  H01L25/16 ,  H01L23/00 ,  H01L25/07

CPC classification number: H02M3/155 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/645 ,  H01L24/16 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/16195 ,  H01L2924/19105 ,  H02M3/00

Abstract: A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

Abstract translation: 电源模块包括基板; 形成在具有特定图案的基板上的导电路径层作为电感器; 连接层形成在所述基板上并电连接到所述电感器的第一端子; 以及第一晶体管，通过连接层电安装在基板上。

公开(公告)号：US08981497B2

公开(公告)日：2015-03-17

申请号：US13548663

申请日：2012-07-13

Applicant: Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

Inventor： Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

IPC: H01L27/14 ,  H01L29/82 ,  H01L29/84 ,  B81B3/00 ,  H01L27/146

CPC classification number: B81B3/0051 ,  B81B2201/025 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.

Abstract translation: 公开了一种用于形成芯片封装结构的芯片封装结构和方法。 至少一个块形成在盖的表面上，盖安装在其上形成有感测装置的基板上，用于覆盖感测装置，并且该块设置在盖和感测装置之间。 在本发明中，该块安装在盖上，不需要蚀刻盖以形成突出部分，因此本发明的方法简单且成本低。

公开(公告)号：US08791768B2

公开(公告)日：2014-07-29

申请号：US13359460

申请日：2012-01-26

Applicant: Ho-Yin Yiu ,  Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Wei-Chung Yang ,  Bai-Yao Lou ,  Hung-Jen Lee

Inventor： Ho-Yin Yiu ,  Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Wei-Chung Yang ,  Bai-Yao Lou ,  Hung-Jen Lee

IPC: H01P5/08 ,  H05K1/18

CPC classification number: H01L23/642 ,  H01L23/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1901 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

Abstract: Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.

Abstract translation: 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。

公开(公告)号：US20130020693A1

公开(公告)日：2013-01-24

申请号：US13548663

申请日：2012-07-13

Applicant: Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

Inventor： Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

IPC: H01L29/02 ,  H01L21/50 ,  H01L21/02

CPC classification number: B81B3/0051 ,  B81B2201/025 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.

Abstract translation: 公开了一种用于形成芯片封装结构的芯片封装结构和方法。 至少一个块形成在盖的表面上，盖安装在其上形成有感测装置的基板上，用于覆盖感测装置，并且该块设置在盖和感测装置之间。 在本发明中，该块安装在盖上，不需要蚀刻盖以形成突出部分，因此本发明的方法简单且成本低。