公开(公告)号：US07339812B2

公开(公告)日：2008-03-04

申请号：US11150349

申请日：2005-06-13

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C5/06

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

摘要： This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US07339811B2

公开(公告)日：2008-03-04

申请号：US11142447

申请日：2005-06-02

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C5/06

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

摘要翻译： 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US20050226041A1

公开(公告)日：2005-10-13

申请号：US11150349

申请日：2005-06-13

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L27/24 ,  G11C11/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

摘要： This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US20050226037A1

公开(公告)日：2005-10-13

申请号：US11142447

申请日：2005-06-02

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

摘要翻译： 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个访问晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US06940748B2

公开(公告)日：2005-09-06

申请号：US10146113

申请日：2002-05-16

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another a plurality of MRAM array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个MRAM阵列层彼此垂直堆叠的多个MRAM单元。

公开(公告)号：US20050162898A1

公开(公告)日：2005-07-28

申请号：US11081652

申请日：2005-03-17

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US06882566B2

公开(公告)日：2005-04-19

申请号：US10895975

申请日：2004-07-22

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US07978491B2

公开(公告)日：2011-07-12

申请号：US12010651

申请日：2008-01-28

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C7/02

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

摘要： This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US07440339B2

公开(公告)日：2008-10-21

申请号：US11142448

申请日：2005-06-02

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C7/10

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

摘要翻译： 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个访问晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US08451642B2

公开(公告)日：2013-05-28

申请号：US13440660

申请日：2012-04-05

申请人： Mirmajid Seyyedy ,  Glen Hush

发明人： Mirmajid Seyyedy ,  Glen Hush

IPC分类号： G11C5/06

CPC分类号： G11C11/1653 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2213/71

摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.