公开(公告)号：US07330367B2

公开(公告)日：2008-02-12

申请号：US11081652

申请日：2005-03-17

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C5/06

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US07042749B2

公开(公告)日：2006-05-09

申请号：US10438344

申请日：2003-05-15

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C7/02

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2213/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

公开(公告)号：US07023743B2

公开(公告)日：2006-04-04

申请号：US10784786

申请日：2004-02-24

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/15

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of cells each column being provided in a respective stacked memory layer.

摘要翻译： 本发明涉及在读取操作期间结合了交叉点和1T-1MTJ架构的某些优点的阵列体系结构。 通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每列的​​多个堆叠列的读数 设置在相应的堆叠存储器层中。

公开(公告)号：US20050162883A1

公开(公告)日：2005-07-28

申请号：US10925243

申请日：2004-08-25

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/16 ,  G11C5/06 ,  G11C17/00

CPC分类号： G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

摘要： A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

摘要翻译： 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US06879516B2

公开(公告)日：2005-04-12

申请号：US10784785

申请日：2004-02-24

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/14

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

公开(公告)号：US20080180982A1

公开(公告)日：2008-07-31

申请号：US12010651

申请日：2008-01-28

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C5/06 ,  G11C11/00 ,  H01L21/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

摘要： This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

公开(公告)号：US07209378B2

公开(公告)日：2007-04-24

申请号：US10925243

申请日：2004-08-25

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

摘要： A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

摘要翻译： 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US20060171224A1

公开(公告)日：2006-08-03

申请号：US11394233

申请日：2006-03-31

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C7/00

CPC分类号： G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

摘要： A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

摘要翻译： 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US20050226038A1

公开(公告)日：2005-10-13

申请号：US11142448

申请日：2005-06-02

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

摘要翻译： 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US06882553B2

公开(公告)日：2005-04-19

申请号：US10214167

申请日：2002-08-08

申请人： Hasan Nejad ,  Mirmajid Seyyedy

发明人： Hasan Nejad ,  Mirmajid Seyyedy

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C7/00

CPC分类号： H01L27/228 ,  G11C5/02 ,  G11C11/16

摘要： This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.

摘要翻译： 本发明涉及一种电阻存储器阵列架构，其结合了在读取操作期间每个单元结构的交叉点和一个晶体管的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的电阻存储器单元的读取，都利用了每个单元架构的一个晶体管的快速读取时间和更高的信噪比以及交叉点架构的较高的堆积密度 每列设置在相应的堆叠存储层中。