公开(公告)号：US09995692B2

公开(公告)日：2018-06-12

申请号：US15015614

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Givantha Iddawela ,  Alok Vaid

IPC: G06F19/00 ,  G01N21/95 ,  G05B19/418 ,  H01L21/66

CPC classification number: G01N21/9501 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/32187 ,  G05B2219/45031 ,  H01L22/10 ,  Y02P90/22

Abstract: Systems and methods for controlling manufacturing processes for microelectronic components are provided. In an exemplary embodiment, a method includes determining a specification range for a desired parameter. The microelectronic component is processed in a manufacturing tool, and a trace data set is recorded during the processing. An estimated trace data parameter is determined with the trace data set, and a first measured value of the microelectronic component is measured in a measurement tool. An estimated desired parameter is determined using the first measured value and the estimated trace data parameter, and the manufacturing process is adjusted when the estimated desired parameter is outside of the specification range.

公开(公告)号：US09281249B2

公开(公告)日：2016-03-08

申请号：US14155504

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alok Vaid ,  Abner Bello ,  Sipeng Gu ,  Lokesh Subramany ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/66 ,  G01B11/02 ,  G01B11/06 ,  G03F7/20 ,  G01N21/21

CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。

公开(公告)号：US09129905B2

公开(公告)日：2015-09-08

申请号：US14070624

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Lokesh Subramany ,  Alok Vaid ,  Sipeng Gu ,  Akshey Sehgal

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/3083 ,  H01L21/3086 ,  H01L22/30 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.

Abstract translation: 公开了一种用于提供与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面计量垫的方法。 先前沉积的非晶碳层可以从预先形成在基底的子集上的心轴上去除，例如使用光致抗蚀剂。 衬垫硬掩模可以在衬底的子集上的心轴上形成。 这种形成导致衬底的子集具有覆盖其上的心轴的衬垫硬掩模，并且具有覆盖其上的心轴的无定形碳层的衬底的其余部分。 该无定形碳层可以在基体的其余部分上从心轴上除去，允许在其中形成一组翅片，而无定形碳层保持该组翅片不会形成在其所覆盖的基底部分中。

公开(公告)号：US09121890B2

公开(公告)日：2015-09-01

申请号：US14067204

申请日：2013-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L21/311 ,  H01L21/302 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract translation: 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US11300948B2

公开(公告)日：2022-04-12

申请号：US16454242

申请日：2019-06-27

Applicant: GLOBALFOUNDRIES INC. ,  NOVA LTD.

Inventor： Taher Kagalwala ,  Alok Vaid ,  Shay Yogev ,  Matthew Sendelbach ,  Paul Isbester ,  Yoav Etzioni

IPC: G05B19/418 ,  G05B13/02

Abstract: A process control method for manufacturing semiconductor devices, including determining a quality metric of a production semiconductor wafer by comparing production scatterometric spectra of a production structure of the production wafer with reference scatterometric spectra of a reference structure of reference semiconductor wafers, the production structure corresponding to the reference structure, the reference spectra linked by machine learning to a reference measurement value of the reference structure, determining a process control parameter value (PCPV) of a wafer processing step, the PCPV determined based on measurement of the production wafer and whose contribution to the PCPV is weighted with a first predefined weight based on the quality metric, and based on a measurement of a different wafer and whose contribution to the PCPV is weighted with a second predefined weight based on the quality metric, and controlling, with the PCPV, the processing step during fabrication.

公开(公告)号：US10121711B2

公开(公告)日：2018-11-06

申请号：US14816708

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L29/10 ,  H01L29/76 ,  H01L21/82 ,  H01L21/66 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

公开(公告)号：US20160239012A1

公开(公告)日：2016-08-18

申请号：US15015614

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Givantha Iddawela ,  Alok Vaid

IPC: G05B19/401

CPC classification number: G01N21/9501 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/32187 ,  G05B2219/45031 ,  H01L22/10 ,  Y02P90/22

Abstract: Systems and methods for controlling manufacturing processes for microelectronic components are provided. In an exemplary embodiment, a method includes determining a specification range for a desired parameter. The microelectronic component is processed in a manufacturing tool, and a trace data set is recorded during the processing. An estimated trace data parameter is determined with the trace data set, and a first measured value of the microelectronic component is measured in a measurement tool. An estimated desired parameter is determined using the first measured value and the estimated trace data parameter, and the manufacturing process is adjusted when the estimated desired parameter is outside of the specification range.

Abstract translation: 提供了用于控制微电子部件的制造工艺的系统和方法。 在示例性实施例中，一种方法包括确定期望参数的规格范围。 在制造工具中处理微电子部件，并且在处理期间记录跟踪数据集。 使用跟踪数据集来确定估计的跟踪数据参数，并且在测量工具中测量微电子部件的第一测量值。 使用第一测量值和估计的跟踪数据参数来确定估计的期望参数，并且当估计的期望参数在规定范围之外时调整制造过程。

公开(公告)号：US20150340296A1

公开(公告)日：2015-11-26

申请号：US14816708

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L21/66 ,  H01L27/088

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract translation: 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US20140273299A1

公开(公告)日：2014-09-18

申请号：US13841919

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Alok Vaid ,  Carsten Hartig

IPC: H01L21/66 ,  G01D21/00

CPC classification number: H01L22/20 ,  G01D3/0365 ,  H01L21/02002 ,  H01L21/67248 ,  H01L21/67276 ,  H01L22/10 ,  H01L22/12 ,  H01L22/26

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.

Abstract translation: 提供了用于制造和测量半导体器件结构的物理特征的方法和系统。 制造半导体器件结构的示例性方法包括从第一计量工具获得半导体器件结构的第一属性的第一测量，通过第一处理工具获得关于制造半导体器件结构的一个或多个特征的处理信息 并且至少部分地基于由所述处理信息影响的方式的所述第一测量来确定所述第一属性的调整的测量。

公开(公告)号：US09903707B2

公开(公告)日：2018-02-27

申请号：US14857914

申请日：2015-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Padraig Timoney ,  Alok Vaid

IPC: H01L21/02 ,  G01B11/06 ,  H01L21/66

CPC classification number: G01B11/06 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: Methodologies and an apparatus for enabling three-dimensional scatterometry to be used to measure a thickness of dielectric layers in semiconductor devices are provided. Embodiments include initiating optical critical dimension (OCD) scatterometry on a three-dimensional test structure formed on a wafer, the three-dimensional test structure comprising patterned copper (Cu) trenches with an ultra-low k (ULK) dielectric film formed over the patterned Cu trenches; and obtaining, by a processor, a thickness of the ULK dielectric film based on results of the OCD scatterometry.