公开(公告)号：US10541300B2

公开(公告)日：2020-01-21

申请号：US15164928

申请日：2016-05-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Yang Sui

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/761 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

公开(公告)号：US20190013311A1

公开(公告)日：2019-01-10

申请号：US15643146

申请日：2017-07-06

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Fabio Carastro ,  Alvaro Jorge Mari Curbelo

IPC: H01L27/06 ,  H01L29/16 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L27/0629 ,  H01L21/8234 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0738 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7802

Abstract: A gate network of a silicon-carbide (SiC) power conversion device includes a plurality of gate electrodes of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device, and a gate pad disposed in a gate pad and bus area of the SiC power conversion device. The gate network also includes a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device. At least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts-per-million per degree Celsius (ppm/° C.).

公开(公告)号：US10096681B2

公开(公告)日：2018-10-09

申请号：US15595611

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/745 ,  H01L29/739 ,  H01L29/74

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20170338303A1

公开(公告)日：2017-11-23

申请号：US15601754

申请日：2017-05-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US09748341B2

公开(公告)日：2017-08-29

申请号：US13934004

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/02 ,  H01L23/58 ,  H01L29/16 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/7802

Abstract: A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device. Further, each the repeating features have a dopant concentration higher than a remainder of the drift layer.

公开(公告)号：US20150372089A1

公开(公告)日：2015-12-24

申请号：US14313820

申请日：2014-06-24

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/10 ,  H01L29/66 ,  H01L27/02 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/1095 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7835

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is not disposed over the center of the semiconductor device cell. The SSBC also includes a source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.

Abstract translation: 在碳化硅（SiC）半导体层的表面上制造半导体器件单元的方法包括在SiC半导体层的表面上形成半导体器件单元的分段源极和体接触（SSBC）。 SSBC包括设置在半导体层的表面上并且靠近半导体器件单元的体接触区域的体接触部分，其中身体接触部分不设置在半导体器件单元的中心上方。 SSBC还包括设置在半导体层的表面上并且靠近半导体器件单元的源极接触区域的源极接触部分，其中至少一个源极接触部分仅部分地围绕SSBC的主体接触部分。

公开(公告)号：US20150008448A1

公开(公告)日：2015-01-08

申请号：US13934004

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/1608 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/7802

Abstract: A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device. Further, each the repeating features have a dopant concentration higher than a remainder of the drift layer.

Abstract translation: 半导体器件包括设置在衬底上的漂移层。 漂移层具有非平面表面，其具有平行于半导体器件的沟道的长度定向的多个重复特征。 此外，每个重复特征的掺杂浓度高于漂移层的其余部分。

公开(公告)号：US10566324B2

公开(公告)日：2020-02-18

申请号：US15599119

申请日：2017-05-18

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/16 ,  H01L23/64 ,  H01L21/82

Abstract: A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors, each having a respective resistance. The device includes a first gate bus extending between the gate pad and the plurality of gate electrodes in a first portion of the active area. The plurality of gate electrodes in the first area is electrically connected to an external gate connection via a first integrated resistor and the first gate bus, and wherein the plurality of gate electrodes in a second portion of the active area is electrically connected to the external gate connection via a second integrated resistor, wherein the first and second integrated resistors have substantially different respective resistance values.

公开(公告)号：US10403623B2

公开(公告)日：2019-09-03

申请号：US15643146

申请日：2017-07-06

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Fabio Carastro ,  Alvaro Jorge Mari Curbelo

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/07

Abstract: A gate network of a silicon-carbide (SiC) power conversion device includes a plurality of gate electrodes of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device, and a gate pad disposed in a gate pad and bus area of the SiC power conversion device. The gate network also includes a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device. At least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts-per-million per degree Celsius (ppm/° C.).

公开(公告)号：US20180337171A1

公开(公告)日：2018-11-22

申请号：US15599119

申请日：2017-05-18

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L27/06 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L29/16 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/04 ,  H01L21/82 ,  H01L23/64

Abstract: A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors, each having a respective resistance. The device includes a first gate bus extending between the gate pad and the plurality of gate electrodes in a first portion of the active area. The plurality of gate electrodes in the first area is electrically connected to an external gate connection via a first integrated resistor and the first gate bus, and wherein the plurality of gate electrodes in a second portion of the active area is electrically connected to the external gate connection via a second integrated resistor, wherein the first and second integrated resistors have substantially different respective resistance values.