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公开(公告)号：US08218370B2
公开(公告)日：2012-07-10
申请号：US13012368
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
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公开(公告)号：US20110182126A1
公开(公告)日：2011-07-28
申请号：US13080814
申请日：2011-04-06
IPC分类号： G11C16/16
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。
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公开(公告)号：US20110116318A1
公开(公告)日：2011-05-19
申请号：US13012361
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
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14.发明授权公开(公告)号：US07944745B2
公开(公告)日：2011-05-17
申请号：US12711520
申请日：2010-02-24
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。
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公开(公告)号：US20110116319A1
公开(公告)日：2011-05-19
申请号：US13012381
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/26
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
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公开(公告)号：US20100149879A1
公开(公告)日：2010-06-17
申请号：US12711520
申请日：2010-02-24
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。
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17.发明授权公开(公告)号：US07688627B2
公开(公告)日：2010-03-30
申请号：US11861102
申请日：2007-09-25
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。
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公开(公告)号：US20080037325A1
公开(公告)日：2008-02-14
申请号：US11565039
申请日：2006-11-30
申请人： Bertram Rogers , Edgardo Laber
发明人： Bertram Rogers , Edgardo Laber
IPC分类号： G11C16/04
CPC分类号： G11C5/145 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006
摘要： Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.
摘要翻译： 提供具有受控上升和下降时间的波形的电路，方法和装置，以及精确的峰值电压。 一个实施例提供用于产生针对片上电容变化而调整的时钟信号和电流的电路。 该电流然后用于产生波形的上升沿和下降沿。 时钟信号用于确定波形中转换的时序。 使用带隙或相似的参考电压来确定峰值电压。 然后使用放大器电路获得该波形，放大器电路的输出用作EE-PROM的编程电压波形。 一个实施例还使用不重叠的时钟来驱动用于产生远远超过可用片上电源电压的放大器电路的电源电压的电荷泵。
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