公开(公告)号：US08797043B2

公开(公告)日：2014-08-05

申请号：US13174040

申请日：2011-06-30

申请人： Edgardo Laber ,  Anthony Allen ,  Carlos Martinez

发明人： Edgardo Laber ,  Anthony Allen ,  Carlos Martinez

IPC分类号： G01R31/02 ,  G01R31/36

CPC分类号： G01R31/026 ,  G01R31/043 ,  G01R31/3658

摘要： An apparatus comprises an integrated circuit and an open connection detection circuit within the integrated circuit. The integrated circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack. The open connection detection circuit within the integrated circuit detects an open connection on at least one of the plurality of inputs from the multi-cell battery and generates a fault condition responsive thereto.

摘要翻译： 一种装置包括集成电路内的集成电路和开路连接检测电路。 集成电路包括用于与多单元电池组的多个输出连接的多个输入。 集成电路内的开路连接检测电路检测来自多单元电池的多个输入中的至少一个上的开路连接，并响应于此产生故障状态。

公开(公告)号：US07903465B2

公开(公告)日：2011-03-08

申请号：US11861111

申请日：2007-09-25

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/0433

摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

公开(公告)号：US20110116324A1

公开(公告)日：2011-05-19

申请号：US13012368

申请日：2011-01-24

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

IPC分类号： G11C16/04

CPC分类号： G11C16/0433

摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

公开(公告)号：US20080266958A1

公开(公告)日：2008-10-30

申请号：US11861102

申请日：2007-09-25

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

公开(公告)号：US20050281115A1

公开(公告)日：2005-12-22

申请号：US11044948

申请日：2005-01-26

申请人： Bertram Rodgers ,  Edgardo Laber

发明人： Bertram Rodgers ,  Edgardo Laber

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C29/02

CPC分类号： G11C5/145 ,  G11C16/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

摘要： Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

摘要翻译： 提供具有受控上升和下降时间的波形的电路，方法和装置，以及精确的峰值电压。 一个实施例提供用于产生针对片上电容变化而调整的时钟信号和电流的电路。 该电流然后用于产生波形的上升沿和下降沿。 时钟信号用于确定波形中转换的时序。 使用带隙或相似的参考电压来确定峰值电压。 然后使用放大器电路获得该波形，放大器电路的输出用作EE-PROM的编程电压波形。 一个实施例还使用不重叠的时钟来驱动用于产生远远超过可用片上电源电压的放大器电路的电源电压的电荷泵。

公开(公告)号：US08325522B2

公开(公告)日：2012-12-04

申请号：US13012361

申请日：2011-01-24

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0433

摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

公开(公告)号：US20080266959A1

公开(公告)日：2008-10-30

申请号：US11861111

申请日：2007-09-25

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

IPC分类号： G11C16/04

CPC分类号： G11C16/0433

摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

公开(公告)号：US06363432B1

公开(公告)日：2002-03-26

申请号：US09280251

申请日：1999-03-29

申请人： Edgardo Laber

发明人： Edgardo Laber

IPC分类号： G06F1300

CPC分类号： H04L12/46

摘要： A technique for interfacing transmission media in a local area network (LAN). A first transceiver and a second transceiver, each have a media dependent interface and a media independent interface. Each media dependent interface is coupled to respective transmission media while the media independent interfaces are coupled together. A receive clock output of the first transceiver is coupled to a first input of a first multiplexer. A receive clock output of the second transceiver is coupled to a first input of a second multiplexer. A fixed frequency clock signal is coupled to a second input of the first multiplexer and to a second input of the second multiplexer. An output of the first multiplexer is coupled to a reference clock input of the second transceiver. An output of the second multiplexer is coupled to a reference clock input of the first transceiver. A select input of the first multiplexer is coupled to a status output of the first transceiver. A select input of the second multiplexer is coupled to a status output of the second transceiver. The reference clock input for each transceiver is selectively coupled to the fixed-frequency clock signal or to the receive clock signal generated by the other transceiver according to whether data is being received from the other transceiver. Accordingly, data is passed from one transceiver to the other without intermediate buffering. Therefore, the invention reduces complexity associated with prior techniques for interfacing transmission media. Preferably, the invention is practiced in a Fast Ethernet LAN.

摘要翻译： 用于在局域网（LAN）中接口传输媒体的技术。 第一收发器和第二收发器各自具有媒体相关接口和媒体独立接口。 每个媒体相关接口耦合到相应的传输媒体，而媒体独立接口耦合在一起。 第一收发器的接收时钟输出耦合到第一多路复用器的第一输入端。 第二收发器的接收时钟输出耦合到第二多路复用器的第一输入端。 固定频率时钟信号耦合到第一多路复用器的第二输入端和第二多路复用器的第二输入端。 第一多路复用器的输出耦合到第二收发器的参考时钟输入。 第二多路复用器的输出耦合到第一收发器的参考时钟输入。 第一多路复用器的选择输入耦合到第一收发器的状态输出。 第二多路复用器的选择输入耦合到第二收发器的状态输出。 根据是否正在从另一收发器接收数据，每个收发器的参考时钟输入选择性地耦合到固定频率时钟信号或由另一收发器产生的接收时钟信号。 因此，数据从一个收发器传递到另一个收发器而不进行中间缓冲。 因此，本发明降低了与用于接口传输介质的现有技术相关联的复杂性。 优选地，本发明在快速以太网LAN中实现。

公开(公告)号：US08345488B2

公开(公告)日：2013-01-01

申请号：US13080814

申请日：2011-04-06

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

公开(公告)号：US08315100B2

公开(公告)日：2012-11-20

申请号：US13012381

申请日：2011-01-24

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

IPC分类号： G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/0433

摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.