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公开(公告)号：US20240163139A1
公开(公告)日：2024-05-16
申请号：US18506544
申请日：2023-11-10
Inventor： Young-deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H04L25/03057 , G06F13/16 , H04L25/0272 , G06F2213/16
Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
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公开(公告)号：US20230115549A1
公开(公告)日：2023-04-13
申请号：US17903112
申请日：2022-09-06
Inventor： Yi-Gyeong KIM , Young-deuk JEON , Young-Su KWON , Jin-Ho HAN
Abstract: Disclosed herein is an apparatus for receiving a strobe signal. The apparatus may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.
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13.发明申请公开(公告)号：US20220172029A1
公开(公告)日：2022-06-02
申请号：US17536536
申请日：2021-11-29
Inventor： In San JEON , Young-Su KWON , Chun-Gi LYUH , Young-deuk JEON , MIN-HYUNG CHO , Jin Ho HAN
Abstract: Disclosed is a simplified sigmoid function circuit which includes a first circuit that performs a computation on input data based on a simplified sigmoid function when a sign of a real region of the input data is positive, a second circuit that performs the computation on the input data based on the simplified sigmoid function when the sign of the real region of the input data is negative, and a first multiplexer that selects and output one of an output of the first circuit and an output of the second circuit, based on the sign of the input data. The simplified sigmoid function is obtained by transforming a sigmoid function of a real region into a sigmoid function of a logarithmic region and performing a variational transformation for the sigmoid function of the logarithmic region.
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公开(公告)号：US20190213471A1
公开(公告)日：2019-07-11
申请号：US16222867
申请日：2018-12-17
Inventor： Young-deuk JEON , Min-Hyung CHO
IPC: G06N3/063
Abstract: Provided is a neuromorphic computing device including a differential signal generator configured to generate a plurality of first differential signals and a plurality of second differential signals on a basis of bits generated according to computation of each of a plurality of pieces of input data and each of a plurality of pieces of weight data corresponding thereto, a first capacitor synapse array configured to sample the plurality of pieces of first differential signals and output a first output voltage, a second capacitor synapse array configured to sample the plurality of pieces of second differential signals and output a second output voltage, a comparator configured to compare the first output voltage with the second output voltage to output a comparison result, and a successive approximation register (SAR) logic configured to control the first capacitor synapse array and the second capacitor synapse array on a basis of the comparison result and generate intermediate data.
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公开(公告)号：US20150131813A1
公开(公告)日：2015-05-14
申请号：US14304156
申请日：2014-06-13
Inventor： Yi-Gyeong KIM , Min-Hyung Cho , Young-deuk JEON , Tae Moon ROH , Woo Seok YANG , Jong-Kee KWON
CPC classification number: H03F1/0266 , H03F3/211 , H03F2200/411 , H04R3/08
Abstract: Provided is a capacitor-type sensor read-out circuit. The capacitor-type sensor read-out circuit includes: a signal conversion unit outputting a sensor signal inputted from a sensor; a voltage booster generating a bias voltage; and a capacitor-type signal coupling circuit receiving the sensor signal as a feedback, mixing the received sensor signal with the bias voltage, and outputting the mixed signal.
Abstract translation: 提供了一种电容式传感器读出电路。 电容式传感器读出电路包括：信号转换单元，输出从传感器输入的传感器信号; 产生偏置电压的升压器; 接收传感器信号作为反馈的电容器型信号耦合电路，将接收到的传感器信号与偏置电压进行混合，并输出混合信号。
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Patent Agency Ranking
16.发明申请WHEEL SPEED SENSOR INTERFACE, OPERATION METHOD THEREOF, AND ELECTRONIC CONTROL SYSTEM INCLUDING THE SAME 有权车轮速度传感器接口，其操作方法和包括其的电子控制系统公开(公告)号：US20150120164A1
公开(公告)日：2015-04-30
申请号：US14259036
申请日：2014-04-22
Inventor： Yi-Gyeong KIM , MIN-HYUNG CHO , Young-deuk JEON , Tae Moon ROH , Jong-Kee KWON
Abstract: Provided is a wheel speed sensor interface. The wheel speed sensor interface includes: a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; and a comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device.
Abstract translation: 提供了一种车轮速度传感器接口。 轮速传感器接口包括：速度脉冲检测电路，被配置为接收包括车辆的车轮速度信息的多个传感器信号，基于多个接收到的传感器信号检测多个速度脉冲，并且发送多个 检测到的速度脉冲到外部设备; 以及比较速度检测电路，被配置为通过对每个所检测的速度脉冲进行计数来生成多个计数值，并通过时分方法多个生成的多个计数值来生成比较速度信息，并将生成的比较速度信息发送到 外部设备。
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公开(公告)号：US20250052860A1
公开(公告)日：2025-02-13
申请号：US18788357
申请日：2024-07-30
Inventor： Young-deuk JEON , Yi-Gyeong KIM , Kyung Hwan PARK , Sujin PARK , MIN-HYUNG CHO
Abstract: Disclosed is a receiver of a radar device, which includes a sampling circuit that receives a reflected pulse signal having a first period reflected from a detection target and samples the reflected pulse signal as a first received signal in response to a clock signal having a second period equal to the first period, an integration circuit that, in response to the clock signal, generates an analog integration signal based on the first received signal and a control signal, a comparison circuit that, in response to the clock signal, adjusts a count value and the control signal based on a result of comparing the analog integration signal with a reference signal and outputs the control signal to the integration circuit, and an ADC circuit that converts the analog integration signal into a digital integration signal.
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公开(公告)号：US20210184677A1
公开(公告)日：2021-06-17
申请号：US16996389
申请日：2020-08-18
Inventor： Min-Hyung CHO , Young-deuk JEON , Seong Min KIM
IPC: H03K19/017 , H03K19/17784 , H03K19/096 , H03K19/08
Abstract: Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.
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公开(公告)号：US20200072665A1
公开(公告)日：2020-03-05
申请号：US16552550
申请日：2019-08-27
Inventor： CHUNWON BYUN , Young-deuk JEON , Chi-Sun HWANG , Chan-mo KANG , Yun-Jeong KIM , Hye Jin KIM , Seongdeok AHN , JEONG IK LEE , Seong Hyun KIM , Bock Soon NA
Abstract: Provided is a pixel circuit. The pixel circuit includes a conversion element configured to form a voltage of an input level corresponding to a magnitude of a received energy at a first node, a first transistor configured to adjust the voltage of the first node to a first level in response to a first signal received at a first time interval, a first capacitive element configured to form a voltage at a second node based on the voltage of the first node, a second transistor configured to adjust a level of the voltage of the second node to a second level in response to the first signal, a third transistor configured to form a voltage at a third node, the voltage having a level corresponding to the level of the voltage of the second node, a fourth transistor configured to output a current corresponding to the voltage of the third node in response to a second signal received in a second time interval after the first time interval, and a fifth transistor configured to adjust the voltage of the third node to a third level in response to a third signal received in a third time interval after the second time interval.
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公开(公告)号：US20190239771A1
公开(公告)日：2019-08-08
申请号：US16248582
申请日：2019-01-15
Inventor： Min-Hyung CHO , Young-deuk JEON , Bon Tae KOO , Mun Yang PARK , Youngseok BAEK
IPC: A61B5/053 , G01N27/02 , G01N33/483 , A61B5/00
CPC classification number: A61B5/0537 , A61B5/4869 , A61B5/7278 , G01N27/028 , G01N33/4833
Abstract: The inventive concept relates to a body composition analysis system. A body composition analysis system according to an embodiment of the inventive concept includes a sinusoidal signal generator, a synchronous detector, and a bioimpedance analyzer. The sinusoidal signal generator converts a digital sinusoidal signal having a target frequency into an analog sinusoidal signal. The synchronous detector extracts a target frequency component of a bioelectrical signal generated in response to an analog sinusoidal signal based on the digital sinusoidal signal. The bioimpedance analyzer calculates the bioimpedance based on the target frequency component of the bioelectrical signal. According to the inventive concept, it is possible to improve the selectivity for extracting the target frequency component of the bioelectrical signal and to reduce the area and variations of characteristics for the implementation of the integrated circuit.
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