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公开(公告)号：US12148383B2
公开(公告)日：2024-11-19
申请号：US18283486
申请日：2021-11-10
Inventor： Yao Huang , Binyan Wang , Zhi Wang , Chao Wu
IPC: G09G3/3233 , G09G3/3266
Abstract: A pixel circuit and a driving method therefor, and a display device are provided. The pixel circuit includes a driving subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, a first switching subcircuit, a second switching subcircuit, a third switching subcircuit, a fourth switching subcircuit and an energy storage subcircuit.
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公开(公告)号：US12020642B2
公开(公告)日：2024-06-25
申请号：US17771073
申请日：2021-02-19
Inventor： Yao Huang , Yuanyou Qiu , Zhi Wang
IPC: G09G3/3233
CPC classification number: G09G3/3233
Abstract: This disclosure provides a display panel and a display device. The display panel includes a light-transmitting area, a first transitional display area, a first main display area and a second main display area, and further includes a first light-emitting unit in the light-transmitting area, a first pixel driving circuit in the first transitional display area for providing a driving current to the first light-emitting unit, a first signal line extending along the column direction in the first main display area, a second signal line extending along the column direction in the second main display area, and a third signal line. The third signal line and the first signal line are in different conductive layers, the third signal line and the second signal line are in different conductive layers, and the third signal line is connected with the first signal line and the second signal line through via holes respectively.
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公开(公告)号：US11537237B2
公开(公告)日：2022-12-27
申请号：US17315643
申请日：2021-05-10
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Shengji Yang , Xue Dong , Xiaochuan Chen , Pengcheng Lu , Lei Wang , Zhi Wang , Weifeng Han , Jing Yu
IPC: G06F3/047 , G06F3/041 , G06F3/044 , G09G3/3233
Abstract: The present disclosure relates to a touch panel. The touch panel includes a plurality of pixel units, and each of the plurality of pixel units includes a pixel circuit. The pixel circuit of each of the plurality of pixel units includes a driver, a writer, a power supply, a reset module, a controller and a compensator. The power supply includes a fourth switching transistor and a second capacitor. A gate of the fourth switching transistor is input with a light emitting control signal, and a source of the fourth switching transistor is input with a power supply signal. The second capacitor includes a first electrode connected to the driver; and a second electrode input with the power supply signal.
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公开(公告)号：US11251207B2
公开(公告)日：2022-02-15
申请号：US16846888
申请日：2020-04-13
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yupeng Gao , Guangcai Yuan , Feng Guan , Zhi Wang , Jianhua Du , Zhaohui Qiang , Chao Li
IPC: H01L27/00 , H01L29/00 , H01L21/00 , H01L27/12 , H01L29/66 , H01L29/786 , H01L29/24 , H01L29/16 , H01L21/84
Abstract: The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.
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公开(公告)号：US11029774B2
公开(公告)日：2021-06-08
申请号：US16029162
申请日：2018-07-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Shengji Yang , Xue Dong , Xiaochuan Chen , Pengcheng Lu , Lei Wang , Zhi Wang , Weifeng Han , Jing Yu
IPC: G06F3/041 , G09G3/3225 , G06F3/044 , G09G3/3233
Abstract: The present disclosure relates to a touch panel and a touch screen. In the touch panel, the cathode is reused. In the touch control stage, each of the cathodes serves as a touch electrode, and normal display and touch functions of the touch panel can be realized by a time-division driving manner. Specifically, in the display stage, the pixel circuit controls the light emitting state of each pixel point (each pixel point has a light emitting device including a cathode); in the touch control stage, touch control signals are applied onto all control signal terminals of the pixel circuit and the cathodes at the same time. By doing so, on the basis that the touch control function can be realized, the synchronous driving of the touch control electrodes and the electrodes corresponding to the touch control electrodes can be realized.
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Patent Agency Ranking
公开(公告)号：US20200185535A1
公开(公告)日：2020-06-11
申请号：US16528622
申请日：2019-08-01
Applicant: BOE Technology Group Co., Ltd.
Inventor： Feng Guan , Guangcai Yuan , Zhi Wang , Chen Xu , Qi Yao , Zhanfeng Cao , Ce Ning , Woobong Lee , Lei Chen
IPC: H01L29/786 , H01L27/12
Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.
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公开(公告)号：US12262608B2
公开(公告)日：2025-03-25
申请号：US17780999
申请日：2021-06-23
Inventor： Jianchang Cai , Chi Yu , Bo Shi , Yudiao Cheng , Zhi Wang , Benlian Wang
IPC: H10K59/131 , H10K59/12 , H10K59/121
Abstract: Disclosed is a display substrate including a base substrate, which includes first and second display regions, and at least one first data line. The first display region includes first and second sub-display regions located on opposite sides of the second display region along a first direction and a third sub-display region located on at least one side of the second display region along a second direction. The first data line includes a first sub-data line located in the first sub-display region and connected with a pixel circuit of the first sub-display region, a second sub-data line located in the second sub-display region and connected with a pixel circuit of the second sub-display region, and a third sub-data line which is connected with the first and second sub-data lines, located in the third sub-display region, and connected with at least one second pixel circuit of the third sub-display region.
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公开(公告)号：US12211858B2
公开(公告)日：2025-01-28
申请号：US18435073
申请日：2024-02-07
Inventor： Qiwei Wang , Yue Long , Zhi Wang , Lili Du , Yuanyou Qiu
Abstract: The display substrate includes: a display area and a bezel area, the display area including a first display area and a second display area; first light emitting devices in the first display area and second light emitting devices in the second display area; first pixel drive circuits in the bezel area and second pixel drive circuits in the second display area, the first pixel drive circuits are connected to the first light emitting devices, and the second pixel drive circuits are connected to the second light emitting devices; and shift registers in the bezel area, one shift register is connected with the first pixel driving circuits connected with one row of the first light emitting devices and the second pixel driving circuits connected with one row of the second light emitting devices.
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19.发明授权公开(公告)号：US11996413B2
公开(公告)日：2024-05-28
申请号：US17413221
申请日：2020-06-09
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhaohui Qiang , Li Qiang , Chao Luo , Huiqin Zhang , Rui Huang , Zhi Wang
IPC: H01L27/12 , H01L29/423 , H01L29/786 , G02F1/1362 , G02F1/1368 , H10K59/121
CPC classification number: H01L27/1222 , H01L27/1248 , H01L27/127 , H01L29/42384 , H01L29/78696 , G02F1/13624 , G02F1/1368 , H10K59/1213
Abstract: A thin film transistor includes a base, a first electrode, an active pattern, a gate insulating layer, a gate and a second electrode. The active pattern includes a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern. A material of one of the first semiconductor pattern and the third semiconductor pattern includes a semiconductor material and N-type doped ions, and a material of another of the first semiconductor pattern and the third semiconductor pattern includes the semiconductor material and P-type doped ions. An orthogonal projection of the gate on the base is non-overlapping with an orthogonal projection of the active pattern on the base.
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公开(公告)号：US11121257B2
公开(公告)日：2021-09-14
申请号：US16641078
申请日：2019-02-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhaohui Qiang , Feng Guan , Zhi Wang , Yupeng Gao , Yang Lyu , Chao Li , Jianhua Du , Lei Chen
IPC: H01L29/786 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/49
Abstract: The present disclosure provides a thin film transistor, a pixel structure, a display device, and a manufacturing method. The thin film transistor includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain respectively connected to the semiconductor layer. The first support portion and the second support portion are respectively configured to support the semiconductor layer.
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