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公开(公告)号：US10113234B2
公开(公告)日：2018-10-30
申请号：US14801348
申请日：2015-07-16
发明人： Bo Xie , Alexandros T. Demos , Vu Ngoc Tran Nguyen , Kelvin Chan , He Ren , Kang Sub Yim , Mehul B. Naik
IPC分类号： C23C16/48 , C23C16/40 , H01L21/768 , H01L21/3105
摘要： Embodiments described herein provide a method for sealing a porous low-k dielectric film. The method includes forming a sealing layer on the porous low-k dielectric film using a cyclic process. The cyclic process includes repeating a sequence of depositing a sealing layer on the porous low-k dielectric film and treating the sealing layer until the sealing layer achieves a predetermined thickness. The treating of each intermediate sealing layer generates more reactive sites on the surface of each intermediate sealing layer, which improves the quality of the resulting sealing layer.
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公开(公告)号：US09793108B2
公开(公告)日：2017-10-17
申请号：US14750778
申请日：2015-06-25
发明人： He Ren , Mehul B. Naik , Deenesh Padhi , Priyanka Dash , Bhaskar Kumar , Alexandros T. Demos
CPC分类号： H01L21/02126 , C23C16/045 , C23C16/36 , C23C16/482 , C23C16/56 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02359 , H01L21/3105 , H01L21/31058 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76831
摘要： A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.
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公开(公告)号：US09305831B2
公开(公告)日：2016-04-05
申请号：US14657827
申请日：2015-03-13
发明人： He Ren , Mehul B. Naik
IPC分类号： H01L21/764 , H01L21/768 , H01L21/3205 , H01L21/311 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/76802 , H01L21/02126 , H01L21/02271 , H01L21/02274 , H01L21/31053 , H01L21/31055 , H01L21/31111 , H01L21/31116 , H01L21/32051 , H01L21/32053 , H01L21/32136 , H01L21/764 , H01L21/7682 , H01L21/76834 , H01L21/76837 , H01L21/76838 , H01L21/76877 , H01L21/76885 , H01L21/76889
摘要： Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.
摘要翻译： 本文所述的实施例涉及形成气隙互连的方法。 金属间隔层共形沉积在其上形成有心轴结构的基底上。 蚀刻金属间隔层以形成间隔件特征，并且将芯棒结构从基底上移除。 可以进行各种其它介电沉积，图案化和蚀刻步骤以期望地存在于基板上的材料。 最终，在相邻间隔物特征之间形成沟槽，并且在沟槽上沉积覆盖层以在相邻间隔物特征之间形成气隙。 为了包装目的，互连通孔可以被配置为接触邻近气隙的间隔件特征中的至少一个。
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14.发明授权Methods for etching a dielectric barrier layer in a dual damascene structure 有权用于蚀刻双镶嵌结构中的电介质阻挡层的方法公开(公告)号：US09299577B2
公开(公告)日：2016-03-29
申请号：US14540577
申请日：2014-11-13
发明人： He Ren , Chia-Ling Kao , Sean Kang , Jeremiah T P Pender , Srinivas D. Nemani , Mehul B. Naik
IPC分类号： H01L21/308 , H01L21/768 , H01L21/311 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/306
CPC分类号： H01L21/308 , H01J37/32357 , H01L21/02063 , H01L21/0234 , H01L21/0332 , H01L21/30604 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.
摘要翻译： 提供了用于消除双镶嵌结构中的导电层的早期暴露并用于蚀刻双镶嵌结构中的介电阻挡层的方法。 在一个实施例中，用于蚀刻设置在衬底上的电介质阻挡层的方法包括使用设置在介电体绝缘层上的硬掩模层作为蚀刻掩模来图案化设置在电介质阻挡层上的介电体绝缘层的衬底， 在去除绝缘体绝缘层未覆盖的绝缘体绝缘层之后，从基板去除硬掩模层，随后蚀刻由绝缘体绝缘层暴露的电介质阻挡层的部分介电阻挡层。
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公开(公告)号：US11990368B2
公开(公告)日：2024-05-21
申请号：US17848162
申请日：2022-06-23
发明人： Mehul B. Naik , Zhiyuan Wu
IPC分类号： H01L21/768 , H01L21/285 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76846 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L21/76879 , H01L21/76882 , H01L21/76883 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L2221/1089
摘要： Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.
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公开(公告)号：US11043415B2
公开(公告)日：2021-06-22
申请号：US16564489
申请日：2019-09-09
发明人： Zhiyuan Wu , Nikolaos Bekiaris , Mehul B. Naik , Jin Hee Park , Mark Hyun Lee
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L21/288 , H01L21/285 , H01L21/67
摘要： In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.
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公开(公告)号：US10727119B2
公开(公告)日：2020-07-28
申请号：US16252100
申请日：2019-01-18
发明人： He Ren , Feiyue Ma , Yu Lei , Kai Wu , Mehul B. Naik , Zhiyuan Wu , Vikash Banthia , Hua Ai
IPC分类号： H01L21/768 , H01L21/285 , H01L23/532 , H01L23/522
摘要： Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.
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公开(公告)号：US10692759B2
公开(公告)日：2020-06-23
申请号：US16037985
申请日：2018-07-17
发明人： Hao Jiang , He Ren , Hao Chen , Mehul B. Naik
IPC分类号： H01L21/768 , H01L21/66 , H01L21/02 , H01L21/033 , H01L21/311 , H01L21/3205 , H01L21/3213 , C23F1/00 , H01L49/02
摘要： Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.
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公开(公告)号：US10566188B2
公开(公告)日：2020-02-18
申请号：US16035983
申请日：2018-07-16
发明人： Maximillian Clemons , Michel Ranjit Frei , Mahendra Pakala , Mehul B. Naik , Srinivas D. Nemani , Ellie Y. Yieh
摘要： Embodiments of the present disclosure generally relate to a film treatment process. In one embodiment, a transition metal oxide layer including a dopant is deposited on a substrate. After the doped transition metal oxide layer is deposited, a high pressure annealing process is performed on the doped transition metal oxide layer to densify the doped transition metal oxide without outgassing of the dopant. The high pressure annealing process is performed in an ambient environment including the dopant and at a pressure greater than 1 bar.
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公开(公告)号：US09865466B2
公开(公告)日：2018-01-09
申请号：US15240410
申请日：2016-08-18
IPC分类号： H01L21/44 , H01L21/285 , H01L21/02 , H01L21/324 , H01L21/768 , H01L23/528
CPC分类号： H01L21/28518 , C23C16/42 , C23C16/4418 , C23C16/511 , C23C16/56 , H01L21/02532 , H01L21/28556 , H01L21/324 , H01L21/76864 , H01L21/76885 , H01L21/76889 , H01L23/528 , H01L23/53271
摘要： Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.
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