公开(公告)号：US11062673B2

公开(公告)日：2021-07-13

申请号：US16587582

申请日：2019-09-30

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G06F1/26 ,  G06G5/00 ,  G06T1/20 ,  G09G5/00 ,  G09G5/18 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/60 ,  G06F1/20 ,  G06T13/80

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US10956220B2

公开(公告)日：2021-03-23

申请号：US15870760

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F1/3206 ,  G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20200273424A1

公开(公告)日：2020-08-27

申请号：US16587582

申请日：2019-09-30

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G09G5/00 ,  G06F1/26 ,  G06T1/20 ,  G09G5/18 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/60

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US10431181B2

公开(公告)日：2019-10-01

申请号：US15471553

申请日：2017-03-28

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G06F5/00 ,  G06F1/26 ,  G09G5/00 ,  G06T1/20 ,  G09G5/18 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/60 ,  G06F1/20 ,  G06T13/80

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US20180349175A1

公开(公告)日：2018-12-06

申请号：US15870760

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10114446B1

公开(公告)日：2018-10-30

申请号：US15284660

申请日：2016-10-04

Applicant: Apple Inc.

Inventor： Patrick Y. Law ,  Robert A. Drebin ,  Keith Cox ,  James S. Ismail

IPC: G06F1/00 ,  G06F1/32

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

公开(公告)号：US09613393B2

公开(公告)日：2017-04-04

申请号：US14821665

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G06F1/20 ,  G06F1/32 ,  G06T1/20 ,  G09G5/00 ,  G09G5/18 ,  G06F1/26

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

公开(公告)号：US09605995B2

公开(公告)日：2017-03-28

申请号：US14472274

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： James S. Ismail

IPC: G01H1/00 ,  G01P15/00

CPC classification number: G01H1/00 ,  G01P15/00

Abstract: The embodiments relate to the use of one or more phase lock loops (PLL's) for detecting wobble of a surface upon which a computing device is set. The PLL's can be configured to lock onto an exponentially-damped sinusoid output from an accelerometer in order to differentiate between surface-induced movement and direct human-induced movement of the computing device. Reduced latency in wobble detection can be achieved by implementing the PLL in software and using multiple PLL's per accelerometer axis. Further reduction in the latency of wobble detection can be achieved by seeding the phase of an oscillator signal generated by each PLL in order to improve phase estimates when attempting to lock a PLL onto the accelerometer output.

公开(公告)号：US11934240B2

公开(公告)日：2024-03-19

申请号：US17664000

申请日：2022-05-18

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Carmel Yamberger ,  Daniele Perretta ,  Jan Krellner ,  Ron Neuman ,  James S. Ismail ,  Keith Cox

IPC: G06F1/28 ,  G06F1/20 ,  G06F11/30

CPC classification number: G06F1/206 ,  G06F1/28 ,  G06F11/3058

Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.

公开(公告)号：US20230376091A1

公开(公告)日：2023-11-23

申请号：US17664000

申请日：2022-05-18

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Carmel Yamberger ,  Daniele Perretta ,  Jan Krellner ,  Ron Neuman ,  James S. Ismail ,  Keith Cox

IPC: G06F1/20 ,  G06F1/28 ,  G06F11/30

CPC classification number: G06F1/206 ,  G06F1/28 ,  G06F11/3058

Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.