公开(公告)号：US11579934B2

公开(公告)日：2023-02-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US11940931B2

公开(公告)日：2024-03-26

申请号：US17141914

申请日：2021-01-05

Applicant: Apple Inc.

Inventor： Jainam A. Shah ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Kushal Dalmia ,  Pierre Habouzit ,  James M. Magee ,  Marina Sadini ,  Daniel A. Steffen

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F12/14 ,  G06F12/0842

CPC classification number: G06F12/1466 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/52 ,  G06F9/526 ,  G06F9/541 ,  G06F9/545 ,  G06F12/0842 ,  G06F2209/5011

Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.

公开(公告)号：US11086800B2

公开(公告)日：2021-08-10

申请号：US16882087

申请日：2020-05-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  Joseph R. Auricchio ,  Russell A. Blaine ,  Daniel A. Chimene ,  Simon M. Douglas ,  Landon J. Fuller ,  Yevgen Goryachok ,  John K. Kim-Biggs ,  Arnold S. Liu ,  James M. Magee ,  Daniel A. Steffen ,  Roberto G. Yepez

IPC: G06F12/14 ,  G06F13/10 ,  G06F13/40 ,  G06F9/54 ,  G06F9/445 ,  G06F13/16

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

公开(公告)号：US11080095B2

公开(公告)日：2021-08-03

申请号：US15870766

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US11048562B2

公开(公告)日：2021-06-29

申请号：US15836459

申请日：2017-12-08

Applicant: Apple Inc.

Inventor： Daniel A. Steffen ,  Pierre Habouzit ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  James M. Magee ,  Puja Gupta

IPC: G06F9/52 ,  G06F9/48

Abstract: Techniques are disclosed relating to efficiently handling execution of multiple threads to perform various actions. In some embodiments, an application instantiates a queue and a synchronization primitive. The queue maintains a set of work items to be operated on by a thread pool maintained by a kernel. The synchronization primitive controls access to the queue by a plurality of threads including threads of the thread pool. In such an embodiment, a first thread of the application enqueues a work item in the queue and issues a system call to the kernel to request that the kernel dispatch a thread of the thread pool to operate on the first work item. In various embodiments, the dispatched thread is executable to acquire the synchronization primitive, dequeue the work item, and operate on it.

公开(公告)号：US20210157748A1

公开(公告)日：2021-05-27

申请号：US17141914

申请日：2021-01-05

Applicant: Apple Inc.

Inventor： Jainam A. Shah ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Kushal Dalmia ,  Pierre Habouzit ,  James M. Magee ,  Marina Sadini ,  Daniel A. Steffen

IPC: G06F12/14 ,  G06F9/48 ,  G06F9/52 ,  G06F9/50 ,  G06F9/54

Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.

公开(公告)号：US20200379804A1

公开(公告)日：2020-12-03

申请号：US16882092

申请日：2020-05-22

Applicant: Apple Inc.

Inventor： Kushal Dalmia ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Nigel R. Gamble ,  James M. Magee ,  Daniel A. Steffen

IPC: G06F9/48 ,  G06F9/50

Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.

公开(公告)号：US10599481B2

公开(公告)日：2020-03-24

申请号：US15870770

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Constantin Pistol ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  Russell A. Blaine ,  Kushal Dalmia

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20200082070A1

公开(公告)日：2020-03-12

申请号：US16664719

申请日：2019-10-25

Applicant: Apple Inc.

Inventor： Bernard J. Semeria ,  Devon S. Andrade ,  Jeremy C. Andrus ,  Ahmed Bougacha ,  Peter Cooper ,  Jacques Fortier ,  Louis G. Gerbarg ,  James H. Grosbach ,  Robert J. McCall ,  Daniel A. Steffen ,  Justin R. Unger

IPC: G06F21/44 ,  H04L9/32 ,  G06F15/78

Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.

公开(公告)号：US20200082069A1

公开(公告)日：2020-03-12

申请号：US16664714

申请日：2019-10-25

Applicant: Apple Inc.

Inventor： Bernard J. Semeria ,  Devon S. Andrade ,  Jeremy C. Andrus ,  Ahmed Bougacha ,  Peter Cooper ,  Jacques Fortier ,  Louis G. Gerbarg ,  James H. Grosbach ,  Robert J. McCall ,  Daniel A. Steffen ,  Justin R. Unger

IPC: G06F21/44 ,  H04L9/32 ,  G06F15/78

Abstract: Embodiments described herein enable the interoperability between processes configured for pointer authentication and processes that are not configured for pointer authentication. Enabling the interoperability between such processes enables essential libraries, such as system libraries, to be compiled with pointer authentication, while enabling those libraries to still be used by processes that have not yet been compiled or configured to use pointer authentication.