公开(公告)号：US11579934B2

公开(公告)日：2023-02-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20150347192A1

公开(公告)日：2015-12-03

申请号：US14290791

申请日：2014-05-29

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  James M. Magee

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  G06F9/4881 ,  G06F2209/5021

Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.

Abstract translation: 在这里描述了用于调度用于在数据处理系统中执行的线程的技术。 根据一个实施例，响应于执行线程的请求，数据处理系统的操作系统的调度器访问全局运行队列以识别与最高进程优先级相关联的全局运行条目。 全局运行队列包括多个全局运行条目，每个条目对应于多个进程优先级中的一个。 基于全局运行条目识别组运行队列，其中组运行队列包括与其中一个进程相关联的多个线程。 调度程序将组运行队列中的线程中具有最高线程优先级的一个线程调度到数据处理系统的一个处理器核心以执行。

公开(公告)号：US10901920B2

公开(公告)日：2021-01-26

申请号：US16380300

申请日：2019-04-10

Applicant: Apple Inc.

Inventor： Jainam A. Shah ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Kushal Dalmia ,  Pierre Habouzit ,  James M. Magee ,  Marina Sadini ,  Daniel A. Steffen

IPC: G06F9/46 ,  G06F12/14 ,  G06F9/48 ,  G06F9/52 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0842

Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.

公开(公告)号：US10671430B2

公开(公告)日：2020-06-02

申请号：US15836411

申请日：2017-12-08

Applicant: Apple Inc.

Inventor： Daniel A. Steffen ,  Jainam A. Shah ,  James M. Magee ,  Jeremy C. Andrus ,  Russell A. Blaine

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54

Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.

公开(公告)号：US20180349176A1

公开(公告)日：2018-12-06

申请号：US15870763

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/505 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4856 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/54 ,  G06F2209/501 ,  G06F2209/5018 ,  G06F2209/509

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US11860796B2

公开(公告)日：2024-01-02

申请号：US17397966

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  Joseph R. Auricchio ,  Russell A. Blaine ,  Daniel A. Chimene ,  Simon M. Douglas ,  Landon J. Fuller ,  Yevgen Goryachok ,  John K. Kim-Biggs ,  Arnold S. Liu ,  James M. Magee ,  Daniel A. Steffen ,  Roberto G. Yepez

IPC: G06F9/54 ,  G06F21/57 ,  G06F13/10 ,  G06F13/40 ,  G06F9/445 ,  G06F13/16

CPC classification number: G06F13/102 ,  G06F9/44505 ,  G06F9/545 ,  G06F9/546 ,  G06F13/1673 ,  G06F13/4072

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

公开(公告)号：US20210318909A1

公开(公告)日：2021-10-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20200379925A1

公开(公告)日：2020-12-03

申请号：US16882087

申请日：2020-05-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  Joseph R. Auricchio ,  Russell A. Blaine ,  Daniel A. Chimene ,  Simon M. Douglas ,  Landon J. Fuller ,  Yevgen Goryachok ,  John K. Kim-Biggs ,  Arnold S. Liu ,  James M. Magee ,  Daniel A. Steffen ,  Roberto G. Yepez

IPC: G06F13/10 ,  G06F13/40 ,  G06F9/54 ,  G06F9/445 ,  G06F13/16

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

公开(公告)号：US20180349186A1

公开(公告)日：2018-12-06

申请号：US15870764

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/50

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US11940931B2

公开(公告)日：2024-03-26

申请号：US17141914

申请日：2021-01-05

Applicant: Apple Inc.

Inventor： Jainam A. Shah ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Kushal Dalmia ,  Pierre Habouzit ,  James M. Magee ,  Marina Sadini ,  Daniel A. Steffen

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F12/14 ,  G06F12/0842

CPC classification number: G06F12/1466 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/52 ,  G06F9/526 ,  G06F9/541 ,  G06F9/545 ,  G06F12/0842 ,  G06F2209/5011

Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.