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    Performance telemetry aided processing scheme
    2.
    发明授权
    Performance telemetry aided processing scheme 有权

    公开(公告)号：US10942850B2

    公开(公告)日：2021-03-09

    申请号：US16513225

    申请日：2019-07-16

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  Aditya Venkataraman ,  Bryan R. Hinch ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Constantin Pistol

    IPC: G06F12/00 ,  G06F12/0802

    Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

    Next fetch prediction return table
    6.
    发明授权
    Next fetch prediction return table 有权

    公开(公告)号：US10445102B1

    公开(公告)日：2019-10-15

    申请号：US15707834

    申请日：2017-09-18

    Applicant: Apple Inc.

    Inventor： Constantin Pistol ,  Ian D. Kountanis

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Systems, apparatuses, and methods for efficient program flow prediction. After receiving a current fetch address, a first predictor performs a lookup of a first table. When the lookup results in a miss and the first table has no available entries, the first predictor overwrites a given entry of the first table with the received fetch address, in response to detecting a strength value for the given entry is below a threshold. Otherwise, in response to detecting no entries of the first table have a strength value below the threshold, the first predictor allocates an entry in the second table for the received fetch address. When an indication of a target address for the received fetch address is a return address for a function call, a third predictor allocates an entry of a third table with the received fetch address.

    Scan-on-fill next fetch target prediction
    8.
    发明授权
    Scan-on-fill next fetch target prediction 有权

    公开(公告)号：US10747539B1

    公开(公告)日：2020-08-18

    申请号：US15350486

    申请日：2016-11-14

    Applicant: Apple Inc.

    Inventor： James Robert Howard Hakewill ,  Constantin Pistol

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

    Abstract: Systems, apparatuses, and methods for instruction next fetch prediction. A scan-on-fill target predictor in a processor generates a predicted next fetch address for the instruction fetch unit. When a group of instructions is used to fill an instruction cache but is not currently being retrieved from the instruction cache for processing by other pipeline stages, the group of instructions are scanned to identify exit points of basic blocks within the group. An entry of a table in the scan-on-fill target predictor is allocated for an instruction in a basic block in the group when the basic block has an exit point with a target address that can be resolved within a single clock cycle. The scan-on-fill target predictor may perform a lookup of the table with the current fetch address. The prediction may be compared to a main branch predictor at a later pipeline stage for training purposes.

    Hardware support for software event collection
    10.
    发明授权
    Hardware support for software event collection 有权

    公开(公告)号：US12182003B1

    公开(公告)日：2024-12-31

    申请号：US17647539

    申请日：2022-01-10

    Applicant: Apple Inc.

    Inventor： Jaidev P. Patwardhan ,  Matthias Knoth ,  Shekhar S. Srikantaiah ,  Prakhar Malhotra ,  Matthew C. Widmann ,  Dmitriy B. Solomonov ,  Constantin Pistol

    IPC: G06F11/36 ,  G06F11/07

    Abstract: An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

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