公开(公告)号：US10747539B1

公开(公告)日：2020-08-18

申请号：US15350486

申请日：2016-11-14

Applicant: Apple Inc.

Inventor： James Robert Howard Hakewill ,  Constantin Pistol

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for instruction next fetch prediction. A scan-on-fill target predictor in a processor generates a predicted next fetch address for the instruction fetch unit. When a group of instructions is used to fill an instruction cache but is not currently being retrieved from the instruction cache for processing by other pipeline stages, the group of instructions are scanned to identify exit points of basic blocks within the group. An entry of a table in the scan-on-fill target predictor is allocated for an instruction in a basic block in the group when the basic block has an exit point with a target address that can be resolved within a single clock cycle. The scan-on-fill target predictor may perform a lookup of the table with the current fetch address. The prediction may be compared to a main branch predictor at a later pipeline stage for training purposes.