公开(公告)号：US12072810B2

公开(公告)日：2024-08-27

申请号：US18475890

申请日：2023-09-27

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US10553274B2

公开(公告)日：2020-02-04

申请号：US16227771

申请日：2018-12-20

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G06F12/0875 ,  G11C8/00 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

公开(公告)号：US10199090B2

公开(公告)日：2019-02-05

申请号：US15271516

申请日：2016-09-21

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G06F12/0875 ,  G11C8/00 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

公开(公告)号：US20160240266A1

公开(公告)日：2016-08-18

申请号：US14621527

申请日：2015-02-13

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael A. Dreesen ,  Edward M. McCombs

IPC: G11C29/04 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C29/04 ,  G11C5/147 ,  G11C7/00 ,  G11C11/417 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5602

Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.

Abstract translation: 公开了对存储器进行干扰测试的方法和装置。 电路可以被配置为将测试数据存储到一个或多个数据存储单元中。 调节电路可以将耦合到一个或多个数据存储单元的电源的电平从第一电平调整到第二电平。 一旦电源的电压电平达到第二电平，电路就可以对一个或多个数据存储单元执行读取操作。 在读取操作完成时，调节电路可以将电源的电压电平恢复到第一电平，并且电路可以执行另一读取操作，其结果可以与测试数据进行比较。

公开(公告)号：US09412469B1

公开(公告)日：2016-08-09

申请号：US14621527

申请日：2015-02-13

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael A. Dreesen ,  Edward M. McCombs

IPC: G11C7/06 ,  G11C7/00 ,  G11C29/04 ,  G11C5/14

CPC classification number: G11C29/04 ,  G11C5/147 ,  G11C7/00 ,  G11C11/417 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5602

Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.

Abstract translation: 公开了对存储器进行干扰测试的方法和装置。 电路可以被配置为将测试数据存储到一个或多个数据存储单元中。 调节电路可以将耦合到一个或多个数据存储单元的电源的电平从第一电平调整到第二电平。 一旦电源的电压电平达到第二电平，电路就可以对一个或多个数据存储单元执行读取操作。 在读取操作完成时，调节电路可以将电源的电压电平恢复到第一电平，并且电路可以执行另一读取操作，其结果可以与测试数据进行比较。

公开(公告)号：US08988107B2

公开(公告)日：2015-03-24

申请号：US13717396

申请日：2012-12-17

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: H03K19/00 ,  H03K19/096 ,  G06F12/10 ,  G11C7/06

CPC classification number: H03K19/096 ,  G06F12/1027 ,  G11C7/062 ,  Y02D10/13

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

Abstract translation: 具有共享门控控制的具有脉冲时钟单元的集成电路包括一个或多个逻辑块，每个逻辑块包括配置成分配时钟信号的时钟分配网络。 该集成电路还包括一个时钟单元，该时钟单元耦合到该一个或多个逻辑块并被配置为产生使用反相逻辑门链形成的脉冲时钟信号。 时钟单元还可以被配置为向时钟分配网络提供脉冲时钟信号。 时钟单元还可以包括耦合到反相逻辑门之一的一个输入的使能输入。 此外，时钟单元可以被配置为响应于使能输入上的使能信号选择性地启用和禁用脉冲时钟信号。

公开(公告)号：US08767495B2

公开(公告)日：2014-07-01

申请号：US14029989

申请日：2013-09-18

Applicant: Apple Inc.

Inventor： Edward M. McCombs ,  Daniel C. Chow ,  Kenneth W. Jones ,  Alexander E. Runas

IPC: G11C7/02

CPC classification number: G11C5/063 ,  G11C7/06 ,  G11C11/4091 ,  G11C2207/002

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract translation: 存储器包括在多个存储阵列之间共享的I / O单元。 共享I / O单元提供阵列的输出数据。 存储器包括连接在每个存储阵列和共享I / O单元之间的隔离单元。 此外，每个存储阵列和共享I / O单元可以通过例如电源门控电路连接到单独的开关电压域。 如果一个或多个存储阵列被置于保持或低电压模式，则耦合到受影响的存储阵列的隔离单元可以被配置为将这些存储阵列的位线与共享的I / O数据路径隔离开来。

公开(公告)号：US20250013576A1

公开(公告)日：2025-01-09

申请号：US18777905

申请日：2024-07-19

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20240111685A1

公开(公告)日：2024-04-04

申请号：US18475890

申请日：2023-09-27

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/14 ,  G11C7/10 ,  G11C8/06 ,  G11C11/419

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US11327896B2

公开(公告)日：2022-05-10

申请号：US16908182

申请日：2020-06-22

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.