公开(公告)号：US20240047228A1

公开(公告)日：2024-02-08

申请号：US17816944

申请日：2022-08-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Sri Ranga Sai Boyapati ,  Deepak Vasant Kulkarni ,  Raja Swaminathan ,  Brett P. Wilkerson ,  Arsalan Alam

IPC: H01L21/48 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/642 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894

Abstract: A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second plated through-hole on the second surface of the component. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US11709327B2

公开(公告)日：2023-07-25

申请号：US17361033

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4274 ,  G02B6/425 ,  G02B6/4255 ,  G02B6/43

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US20230207544A1

公开(公告)日：2023-06-29

申请号：US17560691

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Rahul Agarwal ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.

公开(公告)号：US11911839B2

公开(公告)日：2024-02-27

申请号：US17563830

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Rahul Agarwal ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: B23K20/02 ,  B23K20/24 ,  H01L23/00 ,  H01L25/065 ,  B23K103/00 ,  B23K101/40

CPC classification number: B23K20/02 ,  B23K20/24 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  B23K2101/40 ,  B23K2103/56 ,  H01L25/0657 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/8003 ,  H01L2224/80031 ,  H01L2224/80048 ,  H01L2224/80051 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.

公开(公告)号：US11830817B2

公开(公告)日：2023-11-28

申请号：US17085215

申请日：2020-10-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Rahul Agarwal ,  Raja Swaminathan ,  Michael S. Alfano ,  Gabriel H. Loh ,  Alan D. Smith ,  Gabriel Wong ,  Michael Mantor

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/5381 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688

Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.

公开(公告)号：US20230307405A1

公开(公告)日：2023-09-28

申请号：US17656539

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Lei Fu ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L23/00

CPC classification number: H01L24/24 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/16 ,  H01L24/73 ,  H01L2924/37001 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1427 ,  H01L2924/14252 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/24101 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2224/16137 ,  H01L25/0655

Abstract: An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300° C.

公开(公告)号：US20230197623A1

公开(公告)日：2023-06-22

申请号：US17645104

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Arsalan Alam ,  Raja Swaminathan ,  Rahul Agarwal

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5384 ,  H01L24/14 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5386

Abstract: An electronic device includes a first integrated circuit die, a support structure, and a second integrated circuit die and may include a spacer. The support structure includes a circuit element. The support structure has a thickness of at least 110 microns. The spacer or second integrated circuit die includes a conductor. The spacer or second integrated circuit die is disposed between the first integrated circuit die and the support structure. The conductor is electrically coupled to the integrated circuit die or the circuit element of the support structure. The electronic device provides more flexibility to a designer by allowing a circuit element or circuit that occupies a significant area to be in the support structure.