公开(公告)号：US10311191B2

公开(公告)日：2019-06-04

申请号：US15416731

申请日：2017-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Patrick J. Shyvers ,  Ryan Alan Selby

IPC: G06F17/50 ,  G11C7/06 ,  G11C7/20 ,  G11C5/02

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.

公开(公告)号：US20180165314A1

公开(公告)日：2018-06-14

申请号：US15824771

申请日：2017-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir ,  Patrick J. Shyvers

IPC: G06F17/30

CPC classification number: G06F16/2264 ,  G06F9/3844 ,  G06F16/2246 ,  G06F16/2255

Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of each select bit only once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

公开(公告)号：US20250045206A1

公开(公告)日：2025-02-06

申请号：US18364041

申请日：2023-08-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick J. Shyvers ,  William L. Walker

IPC: G06F12/0871 ,  G06F12/0864

Abstract: An implementation is a method for operating a cache memory in a computing system, receiving a request for a first data item from the cache memory of the computing system, the first data item having an associated tag value. The method also includes performing a lookup in a bloom filter for the tag value associated with the first data item. The method also includes performing a lookup in the cache memory for the requested first data item based on the lookup in the bloom filter. The method also includes updating the bloom filter based on results of the lookup in the cache memory for the requested first data item.

公开(公告)号：US20230096138A1

公开(公告)日：2023-03-30

申请号：US17485178

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick J. Shyvers

IPC: G11C7/22 ,  G11C7/10

Abstract: A processing device is provided which includes a processor and a data storage structure. The data storage structure comprises a data storage array comprising a plurality of lines. Each line comprises at least one A latch configured to store a data bit and a clock gater. The data storage structure also comprises a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines. The data storage structure also comprises a plurality of write index B latches shared by the clock gaters of the lines. The write index B latches are configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.

公开(公告)号：US20190393124A1

公开(公告)日：2019-12-26

申请号：US16563138

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US10509752B2

公开(公告)日：2019-12-17

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G11C5/06 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065 ,  G06F13/40

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

公开(公告)号：US20190332561A1

公开(公告)日：2019-10-31

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H01L25/065

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

公开(公告)号：US10333500B1

公开(公告)日：2019-06-25

申请号：US15883650

申请日：2018-01-30

Applicant: Advanced Micro Devices, Inc.

Inventor： David Scott Vickers ,  Patrick J. Shyvers

IPC: H03K3/037 ,  H03K5/135 ,  G11C11/41 ,  H03K19/177 ,  H03K19/00 ,  H03K19/096 ,  H03K3/57

Abstract: A circuit includes a latch configured to update a stored state of the latch in response to an input data signal and a pulsed clock signal. The circuit includes a pulse generator configured to generate the pulsed clock signal based on an input clock signal, the input data signal, and a feedback signal indicative of a stored state of the latch. The pulse generator may be configured to generate a pulse enable signal based on the input data signal, the input clock signal, and the feedback signal. The pulsed clock signal may be based on the pulse enable signal and the input clock signal. The pulse generator may generate the pulsed clock signal to have a pulse of a first signal level in response to an indication that the stored state of the latch needs to change and generates the pulsed clock signal to have a second signal level, otherwise.