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公开(公告)号：US08554389B2
公开(公告)日：2013-10-08
申请号：US13652709
申请日：2012-10-16
Applicant: BJ Watrous , Apple Inc.
Inventor： Keith Cox , Andrew Bradley Just , Matthew G. Watson , Eric Albert , David Matthew Powers , Daniel Ariel West , Donald J. Novotney , Michael F. Culbert
CPC classification number: G06F1/203 , G06F1/206 , G06F1/3203 , Y02D10/16
Abstract: A thermal manager has a digital filter whose input is to receive raw temperature values from a sensor and whose output is to provide processed or filtered temperature values according to a filter function that correlates temperature at the sensor with temperature at another location in the device. The thermal manager has a look-up table that further correlates temperature at the sensor with temperature at the other location. The look-up table contains a list of processed temperature sensor values, and/or a list of temperatures representing the temperature at the other location, and their respective power consumption change commands. The thermal manager accesses the look-up table using selected, filtered temperature values, to identify their respective power consumption change commands. The latter are then evaluated and may be applied, to mitigate a thermal at the other location. Other embodiments are also described and claimed.
Abstract translation: 热管理器具有数字滤波器，其输入用于从传感器接收原始温度值，其输出是根据将传感器温度与设备中另一位置处的温度相关联的滤波器功能提供经处理或过滤的温度值。 热管理器有一个查找表，进一步将传感器的温度与其他位置的温度相关联。 查找表包含处理的温度传感器值的列表和/或表示其他位置的温度的温度列表及其各自的功率消耗改变命令。 热管理器使用选定的过滤温度值访问查找表，以识别其各自的功耗变化命令。 然后对后者进行评估并且可以被应用，以减轻在另一位置处的热量。 还描述和要求保护其他实施例。
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公开(公告)号：US11960341B2
公开(公告)日：2024-04-16
申请号：US17676665
申请日：2022-02-21
Applicant: Apple Inc.
Inventor： Jamie L. Langlinais , Inder M. Sodhi , Lior Zimet , Keith Cox
IPC: G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3293 , G06F1/3296
CPC classification number: G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3293 , G06F1/3296
Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.
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公开(公告)号：US11822399B2
公开(公告)日：2023-11-21
申请号：US17387376
申请日：2021-07-28
Applicant: Apple Inc.
Inventor： Doron Rajwan , Tal Kuzi , Keith Cox , Yizhang Yang
CPC classification number: G06F1/206 , G06F1/08 , G06F11/3058
Abstract: A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.
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公开(公告)号：US20230060391A1
公开(公告)日：2023-03-02
申请号：US17412230
申请日：2021-08-25
Applicant: Apple Inc.
Inventor： Keith Cox , Jamie L. Langlinais , Inder M. Sodhi
Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level suppl voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.
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公开(公告)号：US11418194B2
公开(公告)日：2022-08-16
申请号：US17399933
申请日：2021-08-11
Applicant: Apple Inc.
Inventor： Keith Cox , Victor Zyuban , Norman J. Rohrer
Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
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Patent Agency Ranking
公开(公告)号：US20210376831A1
公开(公告)日：2021-12-02
申请号：US17399933
申请日：2021-08-11
Applicant: Apple Inc.
Inventor： Keith Cox , Victor Zyuban , Norman J. Rohrer
IPC: H03K19/0175 , H03K5/01 , G11C5/14
Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
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公开(公告)号：US11009938B1
公开(公告)日：2021-05-18
申请号：US16139631
申请日：2018-09-24
Applicant: Apple Inc.
Inventor： Patrick Y. Law , Robert A. Drebin , Keith Cox , James S. Ismail
IPC: G06F1/32 , G06F1/3234 , G06F1/3218 , G06F1/3296 , G06F1/324
Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.
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公开(公告)号：US20210028785A1
公开(公告)日：2021-01-28
申请号：US17008559
申请日：2020-08-31
Applicant: Apple Inc.
Inventor： Keith Cox , Victor Zyuban , Norman J. Rohrer
IPC: H03K19/0175 , H03K5/01 , G11C5/14
Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
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公开(公告)号：US20200379534A1
公开(公告)日：2020-12-03
申请号：US16889232
申请日：2020-06-01
Applicant: Apple Inc.
Inventor： Achmed R. Zahir , Diwakar N. Tundlam , James S. Ismail , Keith Cox , Reza Arastoo , Douglas A. MacKay , John M. Ananny , Michael Eng
IPC: G06F1/28 , G06F1/3212 , H02J7/00 , G01R31/387 , G01R31/367
Abstract: Systems and methods are disclosed for allocating and distributing power management budgets for subsystems (e.g., power usage clients) of a computer system. A power budget allocation subsystem may include a plurality of feedback branches having different associated time constants. Power usage clients with slower power response times may be provided power budgets based on a feedback branch having an associated longer time constant, while power usage clients with faster power response times may be provided with power budgets based on a feedback branch having an associated shorter time constant. The power budgets may be determined in the feedback branches based on power budgeting policies weighting the power budget of each subsystem relative to total power mitigation.
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公开(公告)号：US09672310B1
公开(公告)日：2017-06-06
申请号：US14795013
申请日：2015-07-09
Applicant: Apple Inc.
Inventor： Antonietta Oliva , John G. Dorsey , Keith Cox , Norman J. Rohrer , Sribalan Santhanam , Sung Wook Kang , Mohamed H. Abu-Rama , Ashish R. Jain
CPC classification number: G01R31/2894 , G01R31/2856 , G01R31/2875 , G01R31/2879
Abstract: In an embodiment, the amount of supply voltage guardband to prevent incorrect operation due to aging effects may be modeled using an IC-specific age model generated early in the product life cycle of the IC. For example, high temperature operating life (HTOL) testing may be performed at multiple temperatures and/or voltages to develop the IC-specific age model. The IC-specific age model may be more accurate then the calculations used to develop guardband voltage as discussed previously, which rely on the aging of a single transistor. The IC-specific age model may be used along with monitoring of the aging effects during operation of the IC to predict an amount of increased guardband voltage that is currently desirable to apply to the IC. The predicted amount may vary from about zero when the IC is new to the full amount of guardband voltage when the IC is nearing end of life.
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