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    Global configuration broadcast
    14.
    发明授权
    Global configuration broadcast 有权
    全局配置广播

    公开(公告)号：US09454378B2

    公开(公告)日：2016-09-27

    申请号：US14083010

    申请日：2013-11-18

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

    IPC: G06F3/00 ,  G06F13/00 ,  G06F9/44 ,  G06F3/06 ,  G06F9/445

    CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

    Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

    Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。

    RAW SCALER WITH CHROMATIC ABERRATION CORRECTION
    15.
    发明申请
    RAW SCALER WITH CHROMATIC ABERRATION CORRECTION 审中-公开
    原始尺寸调节器

    公开(公告)号：US20150341604A1

    公开(公告)日：2015-11-26

    申请号：US14679126

    申请日：2015-04-06

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Simon Wolfenden Butler ,  Joseph Anthony Petolino, JR. ,  Joseph P. Bratt

    IPC: H04N9/04 ,  H04N9/64

    Abstract: Systems and methods for down-scaling are provided. In one example, a method for processing image data includes determining a plurality of output pixel locations using a position value stored by a position register, using the current position value to select a center input pixel from the image data and selecting an index value, selecting a set of input pixels adjacent to the center input pixel, selecting a set of filtering coefficients from a filter coefficient lookup table using the index value, filtering the set of source input pixels to apply a respective one of the set of filtering coefficients to each of the set of source input pixels to determine an output value for the current output pixel at the current position value, and correcting chromatic aberrations in the set of source input pixels.

    Abstract translation: 提供了缩小比例的系统和方法。 在一个示例中，用于处理图像数据的方法包括使用位置寄存器存储的位置值来确定多个输出像素位置，使用当前位置值从图像数据中选择中心输入像素并选择索引值，选择 与中心输入像素相邻的一组输入像素，使用索引值从滤波器系数查找表中选择一组滤波系数，对源输入像素组进行滤波，以将滤波系数集合中的相应一个应用于 所述源输入像素的集合以确定当前位置值处的当前输出像素的输出值，以及校正所述源输入像素集合中的色差。

    GLOBAL CONFIGURATION BROADCAST
    16.
    发明申请
    GLOBAL CONFIGURATION BROADCAST 有权
    全球配置广播

    公开(公告)号：US20150095630A1

    公开(公告)日：2015-04-02

    申请号：US14083010

    申请日：2013-11-18

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

    IPC: G06F9/44

    CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

    Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

    Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。

    PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS
    17.
    发明申请
    PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS 有权
    涉及多个虚拟通道的协议转换

    公开(公告)号：US20140304441A1

    公开(公告)日：2014-10-09

    申请号：US13859000

    申请日：2013-04-09

    Applicant: APPLE INC.

    Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Joseph P. Bratt ,  Kevin C. Wong ,  Manu Gulati ,  Rohit K. Gupta

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

    Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。

    Parameter FIFO
    18.
    发明申请
    Parameter FIFO 审中-公开
    参数FIFO

    公开(公告)号：US20140232732A1

    公开(公告)日：2014-08-21

    申请号：US14263424

    申请日：2014-04-28

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet

    IPC: G06T1/60

    CPC classification number: G06T1/60 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/10 ,  G09G2360/12 ,  G09G2360/127

    Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

    Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。

    Raw scaler with chromatic aberration correction
    19.
    发明授权
    Raw scaler with chromatic aberration correction 有权

    公开(公告)号：US10694129B2

    公开(公告)日：2020-06-23

    申请号：US14679126

    申请日：2015-04-06

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Simon Wolfenden Butler ,  Joseph Anthony Petolino, Jr. ,  Joseph P. Bratt

    IPC: G06K9/00 ,  H04N5/367 ,  H04N9/04 ,  H04N9/64 ,  H04N5/232 ,  H04N5/365 ,  H04N1/60 ,  G06T5/00 ,  H04N9/77

    Abstract: Systems and methods for down-scaling are provided. In one example, a method for processing image data includes determining a plurality of output pixel locations using a position value stored by a position register, using the current position value to select a center input pixel from the image data and selecting an index value, selecting a set of input pixels adjacent to the center input pixel, selecting a set of filtering coefficients from a filter coefficient lookup table using the index value, filtering the set of source input pixels to apply a respective one of the set of filtering coefficients to each of the set of source input pixels to determine an output value for the current output pixel at the current position value, and correcting chromatic aberrations in the set of source input pixels.

    Raw Scaler With Chromatic Aberration Correction
    20.
    发明申请
    Raw Scaler With Chromatic Aberration Correction 审中-公开

    公开(公告)号：US20200351460A1

    公开(公告)日：2020-11-05

    申请号：US16907583

    申请日：2020-06-22

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Simon Wolfenden Butler ,  Joseph Anthony Petolino, JR. ,  Joseph P. Bratt

    IPC: H04N5/367 ,  H04N9/04 ,  H04N9/64 ,  H04N5/232 ,  H04N5/365 ,  H04N1/60 ,  G06T5/00 ,  H04N9/77

    Abstract: Systems and methods for down-scaling are provided. In one example, a method for processing image data includes determining a plurality of output pixel locations using a position value stored by a position register, using the current position value to select a center input pixel from the image data and selecting an index value, selecting a set of input pixels adjacent to the center input pixel, selecting a set of filtering coefficients from a filter coefficient lookup table using the index value, filtering the set of source input pixels to apply a respective one of the set of filtering coefficients to each of the set of source input pixels to determine an output value for the current output pixel at the current position value, and correcting chromatic aberrations in the set of source input pixels.

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