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    Memory with expandable row width
    13.
    发明授权
    Memory with expandable row width 有权

    公开(公告)号：US11676659B2

    公开(公告)日：2023-06-13

    申请号：US17530815

    申请日：2021-11-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Wuu ,  Martin Paul Piorkowski

    IPC: G11C7/12 ,  G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/418

    Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

    Memory with expandable row width
    14.
    发明授权
    Memory with expandable row width 有权

    公开(公告)号：US11205477B2

    公开(公告)日：2021-12-21

    申请号：US16996024

    申请日：2020-08-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Wuu ,  Martin Paul Piorkowski

    IPC: G11C11/419 ,  G11C11/418 ,  G11C7/12

    Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

    Configuration of multi-die modules with through-silicon vias
    16.
    发明授权
    Configuration of multi-die modules with through-silicon vias 有权

    公开(公告)号：US10509752B2

    公开(公告)日：2019-12-17

    申请号：US15964647

    申请日：2018-04-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

    IPC: G11C5/06 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065 ,  G06F13/40

    Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

    CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS
    17.
    发明申请
    CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS 审中-公开

    公开(公告)号：US20190332561A1

    公开(公告)日：2019-10-31

    申请号：US15964647

    申请日：2018-04-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

    IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H01L25/065

    Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

    Memory array test logic
    18.
    发明授权
    Memory array test logic 有权
    内存阵列测试逻辑

    公开(公告)号：US09355743B2

    公开(公告)日：2016-05-31

    申请号：US14266039

    申请日：2014-04-30

    Applicant: Advanced Micro Devices Inc.

    Inventor： Amlan Ghosh ,  Keith Allen Kasprak ,  John Wuu ,  John Reginald Riley, III

    IPC: G11C29/02 ,  G11C11/419

    CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5006

    Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

    Abstract translation: 用于静态随机存取存储器（SRAM）阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元，用于存储耦合到多个比特单元的信息，位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。

    VOLTAGE-AWARE SIGNAL PATH SYNCHRONIZATION
    19.
    发明申请
    VOLTAGE-AWARE SIGNAL PATH SYNCHRONIZATION 有权
    电压识别信号路径同步

    公开(公告)号：US20140125381A1

    公开(公告)日：2014-05-08

    申请号：US13668705

    申请日：2012-11-05

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Russell Schreiber ,  John Wuu ,  Keith Kasprak

    IPC: H03K19/00 ,  G06F17/50

    CPC classification number: G06F17/50 ,  G06F13/1689 ,  G06F13/4291 ,  G06F17/5045 ,  G06F2217/62 ,  H03K19/00 ,  H05K3/00

    Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

    Abstract translation: 集成电路（IC）根据其工作电压电平产生时钟延迟控制信号。 时钟延迟控制信号被路由到对应的时钟门控逻辑，其控制相应信号路径的输出的同步捕获。 响应于对应的接收时钟延迟控制的断言，时钟门控逻辑延迟由相应触发器使用的时钟信号。 因此，用于捕获某些信号路径的输出的时钟信号可能在某些电压条件下被延迟。 即使在不同的工作电压条件下不同的信号路径可能表现出不同的相对路径延迟，不同信号路径的这种选择性时钟路径延迟使得IC能够使用更高的时钟频率，或者更可靠地锁定一定时钟频率的路径输出。

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