公开(公告)号：US20150318056A1

公开(公告)日：2015-11-05

申请号：US14266039

申请日：2014-04-30

Applicant: Advanced Micro Devices Inc.

Inventor： Amlan Ghosh ,  Keith Allen Kasprak ,  John Wuu ,  John Reginald Riley, III

IPC: G11C29/02 ,  G11C11/419

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5006

Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Abstract translation: 用于静态随机存取存储器（SRAM）阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元，用于存储耦合到多个比特单元的信息，位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。

公开(公告)号：US09355743B2

公开(公告)日：2016-05-31

申请号：US14266039

申请日：2014-04-30

Applicant: Advanced Micro Devices Inc.

Inventor： Amlan Ghosh ,  Keith Allen Kasprak ,  John Wuu ,  John Reginald Riley, III

IPC: G11C29/02 ,  G11C11/419

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5006

Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Abstract translation: 用于静态随机存取存储器（SRAM）阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元，用于存储耦合到多个比特单元的信息，位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。