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    Nonvolatile semiconductor memory device
    11.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07924615B2

    公开(公告)日：2011-04-12

    申请号：US12714750

    申请日：2010-03-01

    Applicant: Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

    Inventor： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

    IPC: G11C11/34

    CPC classification number: G11C16/3436

    Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

    Abstract translation: 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

    Data processing circuit for contactless IC card
    12.
    发明授权
    Data processing circuit for contactless IC card 有权
    非接触式IC卡数据处理电路

    公开(公告)号：US07652924B2

    公开(公告)日：2010-01-26

    申请号：US12171724

    申请日：2008-07-11

    Applicant: Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

    Inventor： Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

    IPC: G11C16/04

    CPC classification number: G11C5/145 ,  G11C16/12

    Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

    Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
    14.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
    非挥发性半导体存储器件

    公开(公告)号：US20080019162A1

    公开(公告)日：2008-01-24

    申请号：US11758108

    申请日：2007-06-05

    Applicant: Taku OGURA ,  Masaaki Mihara ,  Yoshiki Kawajiri

    Inventor： Taku OGURA ,  Masaaki Mihara ,  Yoshiki Kawajiri

    IPC: G11C5/06

    CPC classification number: G11C11/412 ,  G11C14/00 ,  G11C14/0063

    Abstract: This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.

    Abstract translation: 这种非易失性半导体存储器件包括一个触发器，其中每个由串联连接的负载晶体管和存储晶体管组成的两个反相器是交叉连接的; 以及两个栅极晶体管，每个分别在触发器的一侧分别连接到触发器的节点。 反相器的存储晶体管由存储晶体管构成，其可以通过将电子注入其栅极附近来控制阈值电压。 该非易失性半导体存储装置还包括两个位线，每个位线连接到两个栅极晶体管中的相应一个; 连接到两个栅极晶体管的两个栅电极的字线; 连接到逆变器的存储晶体管的源极的第一电源线; 以及与逆变器的负载晶体管的源极连接的第二电压供给线。

    Large scale integrated circuit with sense amplifier circuits for low voltage operation
    17.
    再颁专利
    Large scale integrated circuit with sense amplifier circuits for low voltage operation 失效
    具有读出放大器电路的大规模集成电路用于低电压操作

    公开(公告)号：USRE37593E1

    公开(公告)日：2002-03-19

    申请号：US09095101

    申请日：1998-06-10

    Applicant: Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    Inventor： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    IPC: G11C700

    CPC classification number: G11C11/4096 ,  G11C5/147 ,  G11C11/406 ,  G11C11/4074

    Abstract: Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

    Abstract translation: 公开了一种单芯片ULSI，其可以在宽范围的电源电压（1V至5.5V）中进行固定操作。 该单芯片ULSI由一个电压转换器电路组成，该电路用于宽范围电源电压的固定内部电压，可适用于多个输入/输出电平的输入/输出缓冲器，一个动态RAM 可以在2V以下的电源电压下工作的这种单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本， 固态摄像机等

    Semiconductor IC device having sense amplifier circuit
    20.
    发明授权
    Semiconductor IC device having sense amplifier circuit 失效
    具有读出放大器电路的半导体IC器件

    公开(公告)号：US5300839A

    公开(公告)日：1994-04-05

    申请号：US865852

    申请日：1992-04-09

    Applicant: Takayuki Kawahara ,  Takesada Akiba ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Kiyoo Itoh ,  Takeshi Sakata

    Inventor： Takayuki Kawahara ,  Takesada Akiba ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Kiyoo Itoh ,  Takeshi Sakata

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: G11C7/065 ,  G11C11/4091 ,  G11C7/062

    Abstract: A sense amplifier circuit is provided for sensing a very small signal includes two MOS transistors responsive to a differential voltage between first and second input signal lines to conduct a differential operation and switches respectively connected between drain regions and gate regions respectively of the two MOS transistors. Before the circuit senses and amplifies the signal, the switches are turned on to generate threshold voltages between the gate regions and the source regions respectively of the two transistors. Consequently, according to the variation in the threshold voltage between the respective transistors, a self-adjustment is achieved on bias voltages of the transistors before the signal amplification. The sense amplifier circuit resultantly develops its operation independent of the variation in the threshold voltage. One use for this sense amplifier circuit is to serve as a sense amplifier for a DRAM.

    Abstract translation: 提供了一种用于感测非常小的信号的读出放大器电路，其包括响应于第一和第二输入信号线之间的差分电压的两个MOS晶体管，以分别连接在两个MOS晶体管的漏极区域和栅极区域之间的差分操作和开关。 在电路感测并放大信号之前，开关导通，以在两个晶体管的栅极区域和源极区域之间产生阈值电压。 因此，根据各个晶体管之间的阈值电压的变化，在信号放大之前对晶体管的偏压进行自调整。 读出放大器电路结果是独立于阈值电压的变化而发展其工作。 该感测放大器电路的一个用途是用作DRAM的读出放大器。

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