公开(公告)号：US5424575A

公开(公告)日：1995-06-13

申请号：US890787

申请日：1992-06-01

申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/73 ,  H01L29/72

CPC分类号： H01L29/7317 ,  H01L27/1203 ,  H01L29/0692

摘要： A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.

摘要翻译： 半导体器件具有形成在绝缘基板上的电绝缘基板和半导体层。 多个半导体区域被定义为彼此接合以在半导体层中形成至少两个同态。 需要具有小厚度的半导体区域之一的引线导体具有特定结构，使得引线导体与半导体层的主表面处的一个半导体区域接触，以在其间进行电连接，并延伸超过该半导体区域 部分半导体层有助于定义除了前述一个半导体区域以外的半导体区域中的至少一个。

公开(公告)号：US4926235A

公开(公告)日：1990-05-15

申请号：US106861

申请日：1987-10-13

申请人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

发明人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

IPC分类号： H01L21/285 ,  H01L21/763 ,  H01L29/423

CPC分类号： H01L21/763 ,  H01L21/28525 ,  H01L29/42304

摘要： A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.

摘要翻译： 公开了一种半导体器件，其包括双极晶体管，每个双极晶体管具有形成在半导体衬底的每个突出部分内的发射极，基极和集电极以及用于器件隔离的沟槽。 双极晶体管和沟槽彼此隔开预定间隔。 根据这种布置，基极接触的宽度变得均匀，并且可以有效地防止晶体管特性的任何变化。

公开(公告)号：US08436333B2

公开(公告)日：2013-05-07

申请号：US11790283

申请日：2007-04-24

申请人： Shinichi Saito ,  Digh Hisamoto ,  Tadashi Arai ,  Takahiro Onai

发明人： Shinichi Saito ,  Digh Hisamoto ,  Tadashi Arai ,  Takahiro Onai

IPC分类号： H01L29/06

CPC分类号： H01L33/34 ,  H01S5/3224

摘要： A light-emitting device according to the present invention includes a first electrode unit for injecting an electron, a second electrode unit for injecting a hole, and light-emitting units and electrically connected to the first electrode unit and the second electrode unit respectively, wherein the light-emitting units and are formed of single-crystal silicon, the light-emitting units and having a first surface (topside surface) and a second surface (underside surface) opposed to the first surface, plane orientation of the first and second surfaces being set to a (100) plane, thicknesses of the light-emitting units and in a direction orthogonal to the first and second surfaces being made extremely thin.

摘要翻译： 根据本发明的发光器件包括用于注入电子的第一电极单元，用于注入孔的第二电极单元和发光单元，并分别与第一电极单元和第二电极单元电连接，其中 所述发光单元由单晶硅形成，所述发光单元具有与所述第一表面相对的第一表面（顶侧表面）和第二表面（下表面），所述第一表面和所述第二表面 设置为（100）面时，发光单元的厚度和与第一表面和第二表面正交的方向的厚度非常薄。

公开(公告)号：US07042051B2

公开(公告)日：2006-05-09

申请号：US10298597

申请日：2002-11-19

申请人： Fumio Ootsuka ,  Takahiro Onai ,  Kazuhiro Ohnishi ,  Shoji Wakahara

发明人： Fumio Ootsuka ,  Takahiro Onai ,  Kazuhiro Ohnishi ,  Shoji Wakahara

IPC分类号： H01L29/78

CPC分类号： H01L29/1083 ,  H01L21/76243 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/12

摘要： Provided is a manufacturing method of a semiconductor device which comprises forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer of a pocket structure, the device of the present invention is suppressed in fluctuations in the threshold voltage. Moreover, with a relative increase in the controllable width of a depletion layer, a sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve a switching rate of the MISFET.

摘要翻译： 提供一种半导体器件的制造方法，其包括在MISFET的沟道区域的整个表面的整个表面上形成杂质浓度分布具有第一峰值的p型杂质层和具有第二峰值的另一p型杂质层 在杂质浓度分布中，每层具有防止穿透的功能。 与具有袋结构的穿通止动层的装置相比，本发明的装置抑制了阈值电压的波动。 此外，随着耗尽层的可控宽度的相对增加，次阈值摆幅变小，从而可以防止阈值电压的降低并提高MISFET的开关率。

公开(公告)号：US07029988B2

公开(公告)日：2006-04-18

申请号：US10936684

申请日：2004-09-09

申请人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

发明人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

IPC分类号： H01L21/76 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/7833

摘要： A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

摘要翻译： 提供了一种用于包含硅 - 锗的硅晶片的浅沟槽隔离的方法和装置。 在一个示例中，该方法包括在表面上含有单晶硅 - 锗层的半导体衬底的硅 - 锗层中形成沟槽区域; 在沟槽区域中形成第一单晶硅层和有源区; 氧化第一单晶硅层; 在所述第一单晶硅层的表面上形成第一热氧化物层; 形成器件隔离区; 在沟槽区域中嵌入绝缘体; 以及在由所述器件隔离区分离的所述单晶硅锗层上的有源区中形成器件，其中在所述有源区中形成所述器件的步骤还包括形成深度的掺杂区域以达到所述单晶硅内 锗层在第一单晶硅层之下。

公开(公告)号：US06982465B2

公开(公告)日：2006-01-03

申请号：US10433786

申请日：2001-12-06

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092

摘要： The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

摘要翻译： 本发明提供一种包括n沟道场效应晶体管和p沟道场效应晶体管的半导体器件，其全部具有优良的漏极电流特性。 在包括n沟道场效应晶体管10和p沟道场效应晶体管30的半导体器件中，覆盖n沟道场效应晶体管10的栅电极15的应力控制膜19经受主要由拉伸应力 。 与n沟道场效应晶体管10的膜19相比，覆盖p沟道场效应晶体管30的栅电极15的应力控制膜39主要由压缩应力引起的膜应力。 因此，预期在n沟道场效应晶体管和p沟道场效应晶体管两者中都会改善漏极电流。 因此，通常可以提高特性。

公开(公告)号：US06878606B2

公开(公告)日：2005-04-12

申请号：US10445927

申请日：2003-05-28

申请人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

发明人： Kazuhiro Ohnishi ,  Nobuyuki Sugii ,  Takahiro Onai

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/7833

摘要： A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

摘要翻译： 提供了一种用于包含硅 - 锗的硅晶片的浅沟槽隔离的方法和装置。 在一个示例中，该方法包括在表面上含有单晶硅 - 锗层的半导体衬底的硅 - 锗层中形成沟槽区域; 在沟槽区域中形成第一单晶硅层和有源区; 氧化第一单晶硅层; 在所述第一单晶硅层的表面上形成第一热氧化物层; 形成器件隔离区; 在沟槽区域中嵌入绝缘体; 以及在由所述器件隔离区分离的所述单晶硅锗层上的有源区中形成器件，其中在所述有源区中形成所述器件的步骤还包括形成深度的掺杂区域以达到所述单晶硅内 锗层在第一单晶硅层之下。

公开(公告)号：US5387545A

公开(公告)日：1995-02-07

申请号：US805969

申请日：1991-12-12

申请人： Yukihiro Kiyota ,  Tohru Nakamura ,  Takahiro Onai ,  Taroh Inada

发明人： Yukihiro Kiyota ,  Tohru Nakamura ,  Takahiro Onai ,  Taroh Inada

IPC分类号： H01L21/22 ,  C30B31/06 ,  H01L21/225 ,  H01L21/331 ,  H01L29/73 ,  H01L21/223

CPC分类号： H01L29/66272 ,  C30B31/06 ,  H01L21/2254 ,  Y10S148/017

摘要： An impurity diffusion method which can control a surface atomic concentration from a low to a high surface atomic concentration with a good uniformity is provided. Natural oxide is removed from the surface of a semiconductor substrate with a deoxidizing atmosphere gas as a diffusion atmosphere gas in advance, and then an impurity gas is passed thereto, while passing the deoxidizing atmosphere gas thereto, thereby conducting the diffusion. Flow rate or concentration of impurity of the impurity gas is so set that the impurity atomic concentration of the diffusion layer can be controlled by the flow rate or the concentration of impurity of the impurity gas. The impurity atomic concentration of the diffusion layer can be controlled by adjusting the flow rate or concentration of impurity of the impurity gas, and a diffusion layer having a low impurity atomic concentration can be formed. A shallow junction having a depth of not more than 50 nm can be formed.

摘要翻译： 提供了能够以均匀性良好地控制表面原子浓度从低到高表面原子浓度的杂质扩散方法。 预先用脱氧气氛气体作为扩散气氛气体从半导体衬底的表面除去天然氧化物，然后在通过脱氧气氛气体的同时通过杂质气体，从而进行扩散。 杂质气体的流量或杂质浓度设定为可以通过杂质气体的流量或杂质浓度来控制扩散层的杂质原子浓度。 扩散层的杂质原子浓度可以通过调节杂质气体的杂质浓度的流量或浓度来进行控制，可以形成杂质原子浓度低的扩散层。 可以形成深度不大于50nm的浅结。

公开(公告)号：US5237200A

公开(公告)日：1993-08-17

申请号：US833759

申请日：1992-02-11

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US5177584A

公开(公告)日：1993-01-05

申请号：US647220

申请日：1991-01-28

申请人： Akihisa Uchida ,  Yuji Yatsuda ,  Katsumi Ogiue ,  Kazuo Nakazato ,  Takahiro Onai

发明人： Akihisa Uchida ,  Yuji Yatsuda ,  Katsumi Ogiue ,  Kazuo Nakazato ,  Takahiro Onai

IPC分类号： H01L27/082

CPC分类号： H01L27/0828

摘要： A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.

摘要翻译： 公开了一种在同一半导体衬底上包括前向双极晶体管和反向双极晶体管的双极性SRAM。 具体地说，反向双极型晶体管的基极区域形成在基板的比前方双极型晶体管的基极区域更深的位置，从而提高反向双极型晶体管的截止频率fT。