公开(公告)号：US20100165722A1

公开(公告)日：2010-07-01

申请号：US12561245

申请日：2009-09-16

Applicant: Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004

Abstract: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.

Abstract translation: 相变存储元件通过逐渐增加/减小的工作电流而结晶化的相变存储器（PCM）。 PCM包括开关电路，相变存储元件，位选择开关，脉冲发生模块和计数模块。 开关电路包括多个开关，选择性地提供到电流源的输出端的分支路径。 位选择开关控制相变存储元件与电流源的输出端之间的导通。 脉冲发生模块输出在高电平和低电压电平之间振荡的脉冲信号。 当使能时，计数模块对脉冲信号的振荡进行计数，并通过一组数字数据输出计数结果。 该组数字数据耦合到开关电路以控制其中的开关。

公开(公告)号：US08508983B2

公开(公告)日：2013-08-13

申请号：US13230865

申请日：2011-09-13

Applicant: Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

Inventor： Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC: G11C11/00

CPC classification number: G11C14/0054

Abstract: A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.

Abstract translation: 提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。 静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。 第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。 第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。 开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由切换线的切换信号控制，以将第一存储装置和第二存储装置导入相同的位线或 相同的补充位线。

公开(公告)号：US20130121058A1

公开(公告)日：2013-05-16

申请号：US13345740

申请日：2012-01-08

Applicant: Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G11C11/00

CPC classification number: G11C8/16 ,  G11C7/14 ,  G11C8/08 ,  G11C8/18 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

Abstract: A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

Abstract translation: 提供了用于控制非易失性存储器的写入定时的电路和方法。 该方法包括以下步骤。 首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。 存储单元存储具有不同电阻状态的数据状态。 通过定时控制线将写时序输入到存储单元。 接下来，基于时钟信号和控制信号来生成写入定时。 写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

公开(公告)号：US08331134B2

公开(公告)日：2012-12-11

申请号：US12853301

申请日：2010-08-10

Applicant: Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

Inventor： Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C14/0054 ,  G11C14/009

Abstract: A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.

Abstract translation: 提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。 第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二开关的第二端子分别连接到第一和第二位线。 第一和第二开关的控制端子连接到字线。 第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二NVM的第二端子分别连接到第一和第二位线。 第一和第二NVM的使能端子连接到使能线。

公开(公告)号：US08300449B2

公开(公告)日：2012-10-30

申请号：US12955657

申请日：2010-11-29

Applicant: Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

Inventor： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

Abstract translation: 提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。 电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。 验证方法包括以下步骤：确定电阻式存储单元是否通过验证。 在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子 信号向电阻存储单元写入反向电压。

公开(公告)号：US20120075908A1

公开(公告)日：2012-03-29

申请号：US12955657

申请日：2010-11-29

Applicant: Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

Inventor： Chih-He Lin ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Pei-Chia Chiang

IPC: G11C11/21

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79

Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

Abstract translation: 提供了一种电阻随机存取存储器（RRAM）及其验证方法。 RRAM包括至少一个电阻存储单元。 电阻存储单元包括电阻存储器元件和晶体管，其中电阻存储器元件的一个端子耦合到晶体管的第一端子。 验证方法包括以下步骤：确定电阻式存储单元是否通过验证。 在第一时间段期间，并且在电阻性存储器单元不能通过验证的情况下，将参考电压施加到电阻性存储元件的另一个端子，并且根据电压将电压脉冲施加到晶体管的第二端子 信号向电阻存储单元写入反向电压。

公开(公告)号：US20120068177A1

公开(公告)日：2012-03-22

申请号：US13308523

申请日：2011-11-30

Applicant: Ra-Min Tain ,  Ming-Ji Dai ,  Shyh-Shyuan Sheu ,  Chih-Sheng Lin ,  Shih-Hsien Wu

Inventor： Ra-Min Tain ,  Ming-Ji Dai ,  Shyh-Shyuan Sheu ,  Chih-Sheng Lin ,  Shih-Hsien Wu

IPC: H01L25/07

CPC classification number: G01B7/18 ,  G01L1/18 ,  G01L1/2206 ,  H01L2224/16145

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Abstract translation: 提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。 第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。 第一电路层设置在第一表面上。 第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。 第二电路层设置在第二表面上。 第一加热器包括串联连接以产生热量的多个第一开关。

公开(公告)号：US20110280073A1

公开(公告)日：2011-11-17

申请号：US12853301

申请日：2010-08-10

Applicant: Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

Inventor： Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

IPC: G11C14/00

CPC classification number: G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C14/0054 ,  G11C14/009

Abstract: A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.

Abstract translation: 提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。 第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二开关的第二端子分别连接到第一和第二位线。 第一和第二开关的控制端子连接到字线。 第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二NVM的第二端子分别连接到第一和第二位线。 第一和第二NVM的使能端子连接到使能线。

公开(公告)号：US07885109B2

公开(公告)日：2011-02-08

申请号：US12273414

申请日：2008-11-18

Applicant: Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/04

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2207/2227 ,  G11C2213/79

Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

Abstract translation: 具有低功耗的存储器和用于抑制存储器的电流泄漏的方法。 存储器的存储单元具有串联耦合的存储元件和晶体管。 当存储器未被访问时，本发明将跨越晶体管的电压设置为零。

公开(公告)号：US20090141548A1

公开(公告)日：2009-06-04

申请号：US12273414

申请日：2008-11-18

Applicant: Wen-Pin LIN ,  Shyh-Shyuan SHEU ,  Lieh-Chiu LIN ,  Pei-Chia CHIANG

Inventor： Wen-Pin LIN ,  Shyh-Shyuan SHEU ,  Lieh-Chiu LIN ,  Pei-Chia CHIANG

IPC: G11C5/14 ,  G11C11/00

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2207/2227 ,  G11C2213/79

Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

Abstract translation: 具有低功耗的存储器和用于抑制存储器的电流泄漏的方法。 存储器的存储单元具有串联耦合的存储元件和晶体管。 当存储器未被访问时，本发明将跨越晶体管的电压设置为零。