公开(公告)号：US20130114325A1

公开(公告)日：2013-05-09

申请号：US13332402

申请日：2011-12-21

Applicant: Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

Inventor： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC: G11C11/00 ,  G11C7/10

CPC classification number: G11C14/009

Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract translation: 提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。 第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。 第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。 第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。 第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。 开关的第二端子耦合到第三电压。

公开(公告)号：US08392132B2

公开(公告)日：2013-03-05

申请号：US12851547

申请日：2010-08-05

Applicant: Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G06F19/00

CPC classification number: G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

Abstract translation: 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US20120320658A1

公开(公告)日：2012-12-20

申请号：US13230865

申请日：2011-09-13

Applicant: Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

Inventor： Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC: G11C11/00

CPC classification number: G11C14/0054

Abstract: A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.

Abstract translation: 提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。 静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。 第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。 第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。 开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由开关线路的开关信号控制，以将第一存储装置和第二存储装置导向同一位线或 相同的补充位线。

公开(公告)号：US20120230099A1

公开(公告)日：2012-09-13

申请号：US13477884

申请日：2012-05-22

Applicant: Shyh-Shyuan SHEU ,  Pei-Chia Chinag ,  Wen-Pin Lin

Inventor： Shyh-Shyuan SHEU ,  Pei-Chia Chinag ,  Wen-Pin Lin

IPC: G11C11/46

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

Abstract translation: 具有可逐渐增加或逐渐减小的工作电流的相变存储器。 相变存储器具有相变存储元件，晶体管和控制电路。 晶体管可操作以调节流过相变存储元件的工作电流。 晶体管具有耦合到电压源的第一端子，耦合到相变存储元件的第二端子以及从控制电路接收控制信号的控制端子。 控制电路专门设计用于将晶体管限制在线性区域。

公开(公告)号：US08199561B2

公开(公告)日：2012-06-12

申请号：US12563971

申请日：2009-09-21

Applicant: Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

Abstract translation: 具有可逐渐增加或逐渐减小的工作电流的相变存储器。 相变存储器具有相变存储元件，晶体管和控制电路。 晶体管可操作以调节流过相变存储元件的工作电流。 晶体管具有耦合到电压源的第一端子，耦合到相变存储元件的第二端子以及从控制电路接收控制信号的控制端子。 控制电路专门设计用于将晶体管限制在线性区域。

公开(公告)号：US07974122B2

公开(公告)日：2011-07-05

申请号：US12485720

申请日：2009-06-16

Applicant: Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

Inventor： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.

Abstract translation: 提供了一种用于相变存储器阵列的验证电路。 感测单元根据使能信号感测来自相变存储器阵列的存储单元的感测电压。 比较器根据感测电压和参考电压产生比较信号，以指示存储器单元是否处于复位状态。 控制单元根据使能信号产生控制信号。 操作单元根据控制信号生成第一信号，以指示比较器是否有效。 调整单元向单元提供写入电流，并且根据控制信号增加写入电流，直到比较信号指示存储单元处于复位状态。

公开(公告)号：US20110122684A1

公开(公告)日：2011-05-26

申请号：US12650544

申请日：2009-12-31

Applicant: Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G11C7/00 ,  G11C11/00 ,  G11C5/14

CPC classification number: G11C11/5678 ,  G11C7/14 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2211/5634

Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

Abstract translation: 提供电压补偿电路，具有该电压补偿电路的多电平存储器件以及用于读取多电平存储器件的电压补偿方法。 当读取存储单元时，根据参考单元的漂移电阻的特性的变化来调整施加到存储器件的参考电压。 参考电压的增加值（即电压差）对应于由漂移条件引起的电阻变化。 漂移补偿机构适应于存储器件的读取驱动器的补偿电路，其可以补偿当从存储器单元读取数据时电压电平的变化。 当发生电阻漂移时，计算漂移量并将其加到参考电压上，以避免当读出存储的数据时由电阻漂移引起的判断误差。

公开(公告)号：US07933147B2

公开(公告)日：2011-04-26

申请号：US11968041

申请日：2007-12-31

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

IPC: G11C11/00

CPC classification number: G11C7/08 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.

Abstract translation: 相变存储器的感测电路。 感测电路包括数据电流源和参考电流源，存储存储器件和参考存储器件，存储开关和参考开关，辅助电流源和比较器。 存储存储器件和参考存储器件的第一端子分别耦合到数据电流源和参考电流源。 存储开关和参考开关分别耦合到存储存储器件和参考存储器件的第二端子。 辅助电流源动态地耦合到存储存储器件和参考存储器件的第一端子。 比较器耦合到存储存储器件和参考存储器件的第一端子。

公开(公告)号：US07787281B2

公开(公告)日：2010-08-31

申请号：US11957044

申请日：2007-12-14

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/00

CPC classification number: G11C13/0061 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.

Abstract translation: 提供了相变存储器写入电路。 该电路包括写入路径和快速写入控制单元。 写入路径还包括电流驱动单元，第一开关器件和相变存储器单元。 电流驱动单元耦合到高电压源并输出驱动电流。 第一开关装置由第一控制信号控制。 快速写入控制单元耦合到写入路径以向写入路径提供写入电压。 当第一开关装置关闭时，快速写入控制单元将写入电压输出到写入路径。 当第一开关装置接通时，快速写入控制单元停止向写入路径输出写入电压。

公开(公告)号：US07768822B2

公开(公告)日：2010-08-03

申请号：US12000981

申请日：2007-12-19

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/00

CPC classification number: G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078

Abstract: One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal.

Abstract translation: 本发明的一个实施例提供一种补偿电路。 补偿电路包括写入驱动器，距离检测电路，操作元件和辅助写入驱动器。 写入驱动器向写入路径提供写入电流。 距离检测电路耦合到写入路径以检测写入电流已经行进的距离，并且基于该距离输出控制信号。 操作元件耦合到写入路径。 辅助写入驱动器基于控制信号向写入路径提供辅助电流。