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公开(公告)号：US12081206B2
公开(公告)日：2024-09-03
申请号：US17951575
申请日：2022-09-23
发明人： Bo-Hao Hsu
摘要： A voltage-mode transmitter includes a serializer, a pre-driver circuit, a driver circuit, and a resistor calibration circuit. The serializer converts a data into a serial data. The pre-driver circuit drives the serial data. The driver circuit includes a slice, a replica slice, a reference voltage generation circuit, a first operational amplifier, and a second operational amplifier. The reference voltage generation circuit is coupled between a first system voltage and a second system voltage and includes a resistor. The resistor calibration circuit is configured to use a first current source and a reference resistor to generate a reference voltage, the first current source being a current source having been calibrated by a bandgap reference (BGR) circuit; to generate a target voltage by causing a current of a second current source to flow through the resistor; and to adjust the resistor according to the reference voltage and the target voltage.
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公开(公告)号：US12068755B2
公开(公告)日：2024-08-20
申请号：US17944340
申请日：2022-09-14
发明人： Shih-Hsiung Huang , Wei-Cian Hong , Sheng-Yen Shih
摘要： A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.
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公开(公告)号：US12068753B2
公开(公告)日：2024-08-20
申请号：US17945481
申请日：2022-09-15
发明人： Yun-Tse Chen , Hsuan-Ting Ho , Liang-Wei Huang , Tzung-Hua Tsai
CPC分类号： H03M1/0617 , H03M1/1023 , H03M1/185
摘要： The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.
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公开(公告)号：US12068598B2
公开(公告)日：2024-08-20
申请号：US17655794
申请日：2022-03-22
发明人： Ching-Lan Yang , Zong-Da Huang , Chun-Yuan Huang
摘要： A power supply circuit is configured to supply power to a display panel. The power supply circuit includes a receiver circuit and a transmitter circuit. The receiver circuit is configured to couple the display panel and output a hot plugging signal. The transmitter circuit is configured to receive the hot plugging signal and couple a power circuit. The transmitter circuit is further configured to communicate the receiver circuit to generate an enable signal. The hot plugging signal and the enable signal are configured to control whether a first voltage signal from the power circuit is transmitted to the receiver circuit and the display panel via the transmitter circuit.
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公开(公告)号：US20240275341A1
公开(公告)日：2024-08-15
申请号：US18416939
申请日：2024-01-19
发明人： SHENG-CIANG TU
CPC分类号： H03F3/245 , H03F1/223 , H03F3/45179 , H03F2200/451 , H03F2200/541
摘要： The present disclosure discloses a power amplification output circuit. An output transformer includes a first side inductor and a second side inductor. A cascode power amplifier is electrically coupled to the first side inductor. An inverter-type power amplifier is electrically coupled to the first side inductor. The cascode power amplifier is activated under a normal power output mode to receive, amplify and output a differential radio frequency input signals from cascode differential input terminals to the output transformer through cascode differential output terminals further to an antenna through the second side inductor. The inverter-type power amplifier is activated under a back off power output mode to receive, amplify and output the differential radio frequency input signals from inverter-type differential input terminals to the output transformer through inverter-type differential output terminals further to the antenna through the second side inductor.
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公开(公告)号：US20240266940A1
公开(公告)日：2024-08-08
申请号：US18412587
申请日：2024-01-14
发明人： Fu-Yi HSIEH , Li-Lung KAO , Chih Kang CHIEN , Chia-Chi TSAI
CPC分类号： H02M1/0083 , H02M7/066 , H02M7/46 , H04S7/30 , H04S2400/15
摘要： A playback circuit including a digital-to-analog converter (DAC), an amplifying output circuit and a control circuit coupled to both is provided. The DAC is configured to convert an input playback audio signal into an input analog playback audio signal according to a first control signal for controlling an upper limit of power consumption of the DAC. The amplifying output circuit is coupled to the DAC and configured to generate an output playback audio signal according to the input analog playback audio signal and a second control signal for controlling an upper limit of power consumption of the amplifying output circuit. The control circuit is configured to generate the first control signal and second control signal according to a volume value of the input playback audio signal, thereby controlling the upper limit of power consumption of the DAC and the upper limit of power consumption of the amplifying output circuit.
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公开(公告)号：US20240266314A1
公开(公告)日：2024-08-08
申请号：US18430689
申请日：2024-02-02
发明人： KAI-YEN CHANG
IPC分类号： H01L23/00 , H01L23/495
CPC分类号： H01L24/48 , H01L23/49503 , H01L23/49541 , H01L2224/48227
摘要： An IC package structure includes a die, a die pad, a downbond wire, a lead frame, and bonding wires. The die includes: a first interference source and a second interference source being coupled with a first signal pad and a second signal pad respectively; and a first grounding pad and a second grounding pad being coupled together and positioned between the two interference sources. The die pad holds the die. The downbond wire couples the second grounding pad with the die pad's grounding terminal. The lead frame includes: a first lead; a second lead; and M grounding lead(s) positioned between the first and second leads. The bonding wires include: a first bonding wire coupling the first signal pad with the first lead; a second bonding wire coupling the second signal pad with the second lead; and N third bonding wire(s) coupling the first grounding pad with the M grounding lead(s).
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公开(公告)号：US12057851B2
公开(公告)日：2024-08-06
申请号：US17946521
申请日：2022-09-16
发明人： Shih-Hsiung Huang , Jun Yang , Yu-Chang Chen
CPC分类号： H03M1/0604 , H03M1/0624 , H03M1/0626 , H03M1/0836 , H03M1/1038 , H03M1/1215 , H03M1/121
摘要： A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.
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公开(公告)号：US12047122B2
公开(公告)日：2024-07-23
申请号：US18162593
申请日：2023-01-31
发明人： Chien-I Chou
CPC分类号： H04B17/102 , H04B1/04 , H04B1/16
摘要： A transmitting circuit, which includes a power amplifier, a processing circuit, and a signal strength indicator circuit. The power amplifier is configured to amplify an input signal according to a power gain of the power amplifier to generate an output signal. The processing circuit is configured to adjust the power gain according to an indicating signal. The signal strength indicator circuit has a plurality of power detection ranges. The signal strength indicator circuit is configured to uses one of the plurality of power detection ranges to detect a power of the output signal to generate the indicating signal.
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公开(公告)号：US12046403B2
公开(公告)日：2024-07-23
申请号：US17035914
申请日：2020-09-29
发明人： Hsiao-Tsung Yen , Ka-Un Chan
CPC分类号： H01F27/2804 , H01F17/0006 , H01F27/29 , H01F2017/0073 , H01F2027/2809 , H01F2027/2819
摘要： A stacked inductor device including an 8-shaped inductor structure a stacked coil. The 8-shaped inductor structure includes a first coil and a second coil. The first coil is disposed in a first area. The first coil includes a first sub-coil and a second sub-coil, and the first sub-coil and the second sub-coil are disposed with an interval circularly with each other. The second coil is disposed in a second area, and the second coil is coupled with the first coil on a boundary between the first area and the second area. The second coil includes a third sub-coil and a fourth sub-coil, and the third sub-coil and the fourth sub-coil are disposed with an interval circularly with each other. The stacked coil is coupled to the first coil and the second coil and is stacked partially on or under the first coil and the second coil.
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