公开(公告)号：US5904553A

公开(公告)日：1999-05-18

申请号：US917119

申请日：1997-08-25

Applicant: Matthias Passlack ,  Jonathan K. Abrokwah ,  Ravi Droopad ,  Brian Bowers

Inventor： Matthias Passlack ,  Jonathan K. Abrokwah ,  Ravi Droopad ,  Brian Bowers

IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: C23C16/45523 ,  C23C16/407 ,  C23C16/455 ,  C23C16/4551 ,  H01L21/31604

Abstract: A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.

Abstract translation: 制造栅极质量氧化物半导体结构的方法包括通过含有氧化镓分子和氧的超音速气体射流在化合物半导体晶片结构的表面上形成绝缘Ga 2 O 3层。 在优选实施例中，具有原子级和化学清洁的半导体表面的III-V族化合物半导体晶片结构经由超高真空准备室从半导体生长室转移到绝缘体沉积室中。 通过超音速气体喷射脉冲引发晶片结构表面上的Ga 2 O 3沉积，并且经历脉冲持续时间，气体射流速度，氧化镓分子和氧原子的摩尔分数以及等离子体能量的优化。

公开(公告)号：US08847280B2

公开(公告)日：2014-09-30

申请号：US13293910

申请日：2011-11-10

Applicant: Jonathan K. Abrokwah ,  Ravindranath Droopad ,  Matthias Passlack

Inventor： Jonathan K. Abrokwah ,  Ravindranath Droopad ,  Matthias Passlack

IPC: H01L29/78 ,  H01L23/31 ,  H01L29/778 ,  H01L29/51 ,  H01L29/207

CPC classification number: H01L29/7783 ,  H01L23/3192 ,  H01L29/207 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Abstract translation: 通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。 在半导体层上形成介电层。 在电介质层上形成密封层并暴露于氧等离子体。 在源 - 漏电极之间的电介质层上形成栅电极。 电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。 希望在密封层的上方设置另外的例如氮化硅的密封层。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

公开(公告)号：US08288798B2

公开(公告)日：2012-10-16

申请号：US13009036

申请日：2011-01-19

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L21/02

CPC classification number: H01L29/1054 ,  H01L29/205 ,  H01L29/22 ,  H01L29/267

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成缓冲层，该缓冲层包含第一化合物半导体，该第一化合物半导体包括元素周期表III-V族之一元素; 和II-VI族。 该方法包括在缓冲层上形成沟道层。 沟道层包含第二化合物半导体，其包括来自周期表的III-V族的元素。 该方法包括在沟道层上形成栅极。 该方法包括在栅极的任一侧上的沟道层的区域上沉积杂质。 该方法包括执行退火处理以激活沟道层中的杂质。

公开(公告)号：US08105925B2

公开(公告)日：2012-01-31

申请号：US12182349

申请日：2008-07-30

Applicant: Jonathan K. Abrokwah ,  Ravindranath Droopad ,  Matthias Passlack

Inventor： Jonathan K. Abrokwah ,  Ravindranath Droopad ,  Matthias Passlack

IPC: H01L21/26

CPC classification number: H01L29/7783 ,  H01L23/3192 ,  H01L29/207 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Abstract translation: 通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230） 所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。 在半导体层（22）上形成介电层（24）。 密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。 在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。 电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。 期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。

公开(公告)号：US07842587B2

公开(公告)日：2010-11-30

申请号：US12022942

申请日：2008-01-30

Applicant: Matthias Passlack ,  Jonathan K. Abrokwah ,  Karthik Rajagopalan ,  Haiping Zhou ,  Richard J. Hill ,  Xu Li ,  David A. Moran ,  Iain G. Thayne ,  Peter Zurcher

Inventor： Matthias Passlack ,  Jonathan K. Abrokwah ,  Karthik Rajagopalan ,  Haiping Zhou ,  Richard J. Hill ,  Xu Li ,  David A. Moran ,  Iain G. Thayne ,  Peter Zurcher

IPC: H01L21/20

CPC classification number: H01L29/78 ,  H01L29/20 ,  H01L29/66462 ,  H01L29/7785

Abstract: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

Abstract translation: 半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。 栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。 金属接触结构（130）形成在晶片衬底上。 接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。 对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。 合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。 然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。

公开(公告)号：US07442654B2

公开(公告)日：2008-10-28

申请号：US11239749

申请日：2005-09-30

Applicant: Ravindranath Droopad ,  Matthias Passlack

Inventor： Ravindranath Droopad ,  Matthias Passlack

IPC: H01L21/31

CPC classification number: H01L21/02266 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28264 ,  H01L21/31604 ,  H01L29/20 ,  H01L29/513 ,  H01L29/78

Abstract: A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.

Abstract translation: 在具有第一表面的支撑半导体结构上形成电介质层结构的方法包括：提供第一氧化物束; 使用第一氧化物束在支撑半导体结构的第一表面上沉积第一层氧化物，其中所述第一氧化物层具有第二表面; 终止第一氧化物束，并且同时提供第二氧化物束，金属梁和氧束，其中所述第一和第二氧化物束是分离的和不同的氧化物束; 以及使用所述第二氧化物束，所述金属束和所述氧束将所述第二表面的氧化物沉积在所述第二表面上。

公开(公告)号：US07429506B2

公开(公告)日：2008-09-30

申请号：US11236186

申请日：2005-09-27

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/20

CPC classification number: H01L29/41775 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/7725

Abstract: A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconductor substrate proximate opposite sides of the active device region, and forming a gate metal contact electrode on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts having portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure an avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.

Abstract translation: 一种形成化合物半导体器件的方法包括形成覆盖在化合物半导体衬底上的栅极绝缘体层，在化合物半导体衬底内限定有源器件区域，在化学半导体衬底的邻近有源器件区域的相对侧上形成欧姆接触，以及形成 在欧姆接触之间的区域中的栅极绝缘体层上的栅极金属接触电极。 欧姆接触件具有与有源器件区域内的栅极绝缘体层的部分重叠的部分。 重叠部分确保避免在欧姆接触的边缘和栅极绝缘体层的相应边缘之间形成不期望的间隙。

公开(公告)号：US07202182B2

公开(公告)日：2007-04-10

申请号：US10882482

申请日：2004-06-30

Applicant: Matthias Passlack ,  Nicholas Medendorp

Inventor： Matthias Passlack ,  Nicholas Medendorp

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/3105 ,  H01L21/28264

Abstract: The present invention provides a method of passivating an oxide compound disposed on a III-V semiconductor substrate. The method is intended for use with dielectric stacks, gallate compounds, and gallium compounds used in gate quality oxide layers. The method includes heating a semiconductor structure at an elevated temperature of between about 230° C. and about 400° C. The semiconductor structure is exposed to an atmosphere that is supersaturated with water vapor or vapor of deuterium oxide. The exposure takes place at elevated temperature and continues for a period of time between about 5 minutes to about 120 minutes. It has been found that the method of the present invention results in a semiconductor product that has significantly improved performance characteristics over semiconductors that are not passivated, or that use a dry hydrogen method of passivation.

Abstract translation: 本发明提供一种钝化设置在III-V半导体衬底上的氧化物的方法。 该方法旨在用于栅极质量氧化物层中使用的电介质叠层，没食子酸酯化合物和镓化合物。 该方法包括在约230℃和约400℃之间的升高的温度下加热半导体结构。将半导体结构暴露于用水蒸气或氧化氘蒸气过饱和的气氛中。 曝光在升高的温度下进行，并持续约5分钟至约120分钟之间的时间。 已经发现，本发明的方法产生了与不被钝化的半导体相比具有明显改善的性能特性的半导体产品，或者使用干法氢化钝化方法。

公开(公告)号：US20060022217A1

公开(公告)日：2006-02-02

申请号：US10903784

申请日：2004-07-30

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L31/0328 ,  H01L29/76

CPC classification number: H01L29/51 ,  H01L21/823814 ,  H01L27/0605

Abstract: A complementary metal-oxide-semiconductor field effect transistor structure includes ion implants in only one of the two complementary devices. The transistor structure generally includes a compound semiconductor substrate and an epitaxial layer structure that includes one or more donor layers that establish a conductivity type for the epitaxial layer structure. The ion implants function to “invert” or “reverse” the conductivity type of the epitaxial layer structure in one of the complementary devices. In the example embodiment, p-type acceptor implants are utilized in the p-channel device, while the n-channel device remains implant-free.

Abstract translation: 互补金属氧化物半导体场效应晶体管结构仅包括两个互补器件中的一个中的离子注入。 晶体管结构通常包括化合物半导体衬底和外延层结构，该外延层结构包括建立外延层结构的导电类型的一个或多个施主层。 离子注入功能在互补器件之一中“反转”或“反转”外延层结构的导电类型。 在示例性实施例中，p型受体植入物用于p沟道器件，而n沟道器件保持无植入。

公开(公告)号：US20050221623A1

公开(公告)日：2005-10-06

申请号：US11136845

申请日：2005-05-25

Applicant: Matthias Passlack ,  Nicholas Medendorp

Inventor： Matthias Passlack ,  Nicholas Medendorp

IPC: C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/28 ,  H01L21/31 ,  H01L21/316 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga—Gd-oxide provides a low oxide leakage current density.