公开(公告)号：US06103455A

公开(公告)日：2000-08-15

申请号：US73947

申请日：1998-05-07

Applicant: Kuo Ching Huang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Kuo Ching Huang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/768 ,  G03F7/26

CPC classification number: H01L21/76876 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7688

Abstract: A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.

Abstract translation: 通过在半导体结构10上形成电介质层20来形成深度接触的方法。主要的一点是在形成插头52之后去除硬掩模30。 在电介质层20上形成硬掩模层30.在硬掩模层30之上形成接触光刻胶层36.硬掩模层30通过接触光致抗蚀剂开口39蚀刻以形成接触硬掩模开口41， 电介质层20.使用接触光致抗蚀剂层36和硬掩模层30作为在电介质层20中形成接触孔40的蚀刻掩模的高密度等离子体蚀刻工艺来蚀刻电介质层20.接触光致抗蚀剂层36是 删除。 形成填充接触孔40并覆盖在硬掩模层30上的金属层50.金属层50被回蚀，形成填充接触孔40的插塞52.现在，去除硬掩模层30。 在金属层50沉积之后去除硬掩模30：（a）防止接触孔40在硬掩模30去除步骤期间被光致抗蚀剂和其它污染物污染; 和（b）产生不具有凹部的插头52。

公开(公告)号：US6093619A

公开(公告)日：2000-07-25

申请号：US99809

申请日：1998-06-18

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Chia-Shiung Tsai

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Chia-Shiung Tsai

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/76895

Abstract: A new method of forming a buried contact junction in a process involving shallow trench isolation is described. A first silicon oxide layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. An opening is etched in the first silicon nitride and pad oxide layers where they are not covered by a mask. The substrate underlying the opening is etched into to form a shallow trench. An oxide material is deposited over the surface of the first silicon nitride layer and within the shallow trench and planarized to the surface of the first silicon nitride layer wherein the oxide material forms a STI region. The first silicon nitride layer is removed whereby the STI protrudes above the pad oxide layer. The pad oxide layer is removed whereby the corners of the STI above the substrate are also removed. A second silicon nitride layer is deposited overlying a sacrificial oxide layer and etched away to leave silicon nitride spacers filling in and rounding the corners of the STI. The sacrificial oxide layer is removed. A gate electrode and source/drain regions are formed in and on the substrate wherein a source/drain is adjacent to the STI. The gate electrode and STI are covered with an insulating layer. An opening is etched through the insulating layer to the source/drain region wherein the silicon nitride spacer at the corner of the STI prevents etching of the STI. The opening is filled with a conducting layer to complete formation of a contact.

Abstract translation: 描述了在涉及浅沟槽隔离的过程中形成掩埋接触结的新方法。 在半导体衬底的表面上的衬垫氧化物层上沉积第一氧化硅层。 在第一氮化硅和衬垫氧化物层中蚀刻开口，其中它们不被掩模覆盖。 蚀刻开口下方的基板以形成浅沟槽。 氧化物材料沉积在第一氮化硅层的表面上并在浅沟槽内，并且平坦化到第一氮化硅层的表面，其中氧化物材料形成STI区域。 去除第一氮化硅层，由此STI突出到衬垫氧化物层的上方。 移除衬垫氧化物层，从而也去除衬底上方的STI的拐角。 将第二氮化硅层沉积在牺牲氧化物层上并被蚀刻掉以留下氮化硅间隔物填充到STI的角部并使其四周。 去除牺牲氧化物层。 栅极电极和源极/漏极区域形成在衬底中和衬底上，其中源极/漏极与STI相邻。 栅电极和STI被绝缘层覆盖。 通过绝缘层蚀刻开口到源极/漏极区域，其中STI的拐角处的氮化硅间隔物防止STI的蚀刻。 开口填充有导电层以完成接触的形成。

公开(公告)号：US6078087A

公开(公告)日：2000-06-20

申请号：US379230

申请日：1999-08-23

Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

IPC: H01L21/8244 ,  H01L27/11 ,  H07L27/11

CPC classification number: H01L27/11 ,  H01L27/1108 ,  Y10S257/903

Abstract: A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region. A doped interconnect line is also formed in the polysilicon conductive layer. There is a contact which extends through the gate oxide layer between the interconnection line and the polysilicon conductive layer.

Abstract translation: MOSFET SRAM器件中的导体和衬底区域之间的接触由部分完成的SRAM器件的表面上的介电层形成，该器件具有传输晶体管和锁存晶体管，其中介电层形成在那些通过和锁存晶体管之上。 在电介质层的上表面上形成薄膜晶体管栅电极和互连线。 栅极氧化层覆盖栅电极和互连线。 覆盖栅极氧化物层的多晶硅导电层包括形成在沟道区域的相对侧上的源极区域和漏极区域之间的沟道区域。 存在与形成在沟道区域上方的沟道区域以及栅极电极之上自对准的沟道掩模。 在沟道掩模之外掺杂多晶硅导电层，从而在沟道区的相对侧上提供源极区和漏极区。 掺杂的互连线也形成在多晶硅导电层中。 存在在互连线和多晶硅导电层之间延伸通过栅极氧化物层的接触。

公开(公告)号：US6033985A

公开(公告)日：2000-03-07

申请号：US102374

申请日：1998-06-30

Applicant: Yean-Kuen Fang ,  Kuo-Ching Huang ,  Chung-Yao Chen

Inventor： Yean-Kuen Fang ,  Kuo-Ching Huang ,  Chung-Yao Chen

IPC: H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8234

CPC classification number: H01L21/76855 ,  H01L21/76843 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1108

Abstract: A contact process interconnects poly-crystal silicon layer, and more particularly, this process dramatically decreases the voltage drop within a poly-crystal silicon layer. The advantages of the process include not only improvement in the interface quality of Poly-Si/SiO2 to decrease the junction damage but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM to meet high integration requirement in VLSI.

Abstract translation: 接触工艺互连多晶硅层，更具体地说，该工艺显着地降低了多晶硅层内的电压降。 该工艺的优点不仅在于改善Poly-Si / SiO 2的界面质量以减少接合损伤，而且在制造多晶硅薄膜SRAM期间不会增加其工艺复杂性及其掩模编号以满足 VLSI高集成度要求。

公开(公告)号：US6027969A

公开(公告)日：2000-02-22

申请号：US090497

申请日：1998-06-04

Applicant: Kuo Ching Huang ,  James Wu

Inventor： Kuo Ching Huang ,  James Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

Abstract translation: 已经开发了用于增加DRAM层叠电容器结构的表面积以及因此增加电容的方法。 通过使用多个多晶硅和绝缘体沉积，以及通过使用干各向异性和湿各向同性的蚀刻工艺，创建了包含多晶硅分支的存储节点电极。 在硅氧化物台面的侧面产生的多晶硅间隔物的使用增加了多晶硅分支的垂直分量。 从多晶硅分支之间去除绝缘体层的一部分导致增加的存储节点电极表面积的暴露。 在多晶硅分支之间的绝缘体层的未蚀刻部分为存储节点电极提供由多晶硅分支组成的结构支撑。

公开(公告)号：US4688402A

公开(公告)日：1987-08-25

申请号：US902203

申请日：1986-08-29

Applicant: Kuo-Ching Huang

Inventor： Kuo-Ching Huang

IPC: D04B15/88

CPC classification number: D04B15/38 ,  D04B15/88

Abstract: An improved transmission mechanism assembly for knitting machines having a shaft structure and gear combination mounted at the lower end of the transmission mechanism. The transmission mechanism incorporates an electronically controlled magnetic relay. When the base and mouth of knitted bags require high density knitting in order to form reinforced belts, cessation of fabric takeup during knitting processes can be performed on the knitted bag in order to form reinforced belts. As a result, rigid PP or PE knitted bags can be easily and conveniently made.

Abstract translation: 一种用于具有安装在传动机构的下端的轴结构和齿轮组合的针织机的改进的传动机构组件。 传动机构包含电子控制的磁性继电器。 当针织袋的基部和口部需要高密度编织以形成加强带时，可以在针织袋上进行编织过程中的织物卷绕，以形成加强带。 因此，可以容易地制造刚性PP或PE编织袋。

公开(公告)号：US08853021B2

公开(公告)日：2014-10-07

申请号：US13273012

申请日：2011-10-13

Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

Abstract translation: 提供了一种用于电气设备的嵌入式晶体管，例如DRAM存储单元及其制造方法。 在衬底中形成沟槽，并且在衬底的沟槽中形成栅极电介质和栅电极。 源极/漏极区域形成在沟槽的相对侧上的衬底中。 在一个实施例中，源极/漏极区域中的一个耦合到存储节点，而另一个源极/漏极区域耦合到位线。 在该实施例中，栅电极可以耦合到字线以形成DRAM存储单元。

公开(公告)号：US08825122B2

公开(公告)日：2014-09-02

申请号：US13239359

申请日：2011-09-21

Applicant: Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

Inventor： Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

IPC: H05K7/00 ,  G06F1/16 ,  H05K5/02 ,  H04M1/02

CPC classification number: G06F1/1624 ,  H04M1/0237 ,  H04M1/0239

Abstract: A hand-held device includes a first body, a second body, a sliding module, and a guiding module. The sliding module is disposed between the first body and the second body, so that the second body is able to be slid on a two-dimensional plane relative to the first body. The guiding module includes a first guiding part and a second guiding part. The first guiding part is fixed to the first body. The second guiding part is fixed to the second body and coupled to the first guiding part. Besides, the second guiding part is able to be moved along a guiding path relative to the first guiding part, so that the second body is able to be slid along the guiding path on the two-dimensional plane relative to the first body.

Abstract translation: 手持式装置包括第一主体，第二主体，滑动模块和引导模块。 滑动模块设置在第一主体和第二主体之间，使得第二主体能够相对于第一主体在二维平面上滑动。 引导模块包括第一引导部分和第二引导部分。 第一个引导部分固定在第一个身体。 第二引导部分固定到第二主体并且联接到第一引导部分。 此外，第二引导部能够相对于第一引导部沿着引导路径移动，使得第二主体能够相对于第一主体沿着二维平面上的引导路径滑动。

公开(公告)号：US07847847B2

公开(公告)日：2010-12-07

申请号：US11044922

申请日：2005-01-27

Applicant: Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

Inventor： Dun-Nian Yaung ,  Kuo-Ching Huang ,  Ho-Ching Chien ,  Shou-Gwo Wuu

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/361 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

Abstract: A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.

Abstract translation: 提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。 增加的电容可以降低噪声和暗信号。 图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。 附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。 本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

公开(公告)号：US20090051034A1

公开(公告)日：2009-02-26

申请号：US11892103

申请日：2007-08-20

Applicant: Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

Inventor： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L27/10888 ,  H01L21/76844

Abstract: A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.

Abstract translation: 提供一种形成半导体器件的方法。 该方法包括以下步骤。 提供具有第一触点的基板。 在基板上形成层状结构。 形成层状结构中的凹部以暴露第一接触件的至少一部分。 在层状结构和第一接触的至少一部分上形成胶层。 胶层从第一接触件的至少一部分去除。 形成接触第一接触和胶层的第二接触。