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    Embedded transistor
    1.
    发明授权
    Embedded transistor 有权
    嵌入式晶体管

    公开(公告)号：US08853021B2

    公开(公告)日：2014-10-07

    申请号：US13273012

    申请日：2011-10-13

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108

    CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

    Abstract translation: 提供了一种用于电气设备的嵌入式晶体管，例如DRAM存储单元及其制造方法。 在衬底中形成沟槽，并且在衬底的沟槽中形成栅极电介质和栅电极。 源极/漏极区域形成在沟槽的相对侧上的衬底中。 在一个实施例中，源极/漏极区域中的一个耦合到存储节点，而另一个源极/漏极区域耦合到位线。 在该实施例中，栅电极可以耦合到字线以形成DRAM存储单元。

    Method of forming an embedded memory device
    3.
    发明授权
    Method of forming an embedded memory device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US09082705B2

    公开(公告)日：2015-07-14

    申请号：US13566710

    申请日：2012-08-03

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Method of Forming an Embedded Memory Device
    5.
    发明申请
    Method of Forming an Embedded Memory Device 有权
    形成嵌入式存储器件的方法

    公开(公告)号：US20140035020A1

    公开(公告)日：2014-02-06

    申请号：US13566710

    申请日：2012-08-03

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang ,  Chih-Yang Pai

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/42356 ,  H01L29/66833 ,  H01L29/792

    Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

    Abstract translation: 本公开描述了形成存储器件的方法。 该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极， 以及在所述控制多晶堆叠图案中形成控制栅极。 形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

    Embedded Transistor
    6.
    发明申请
    Embedded Transistor 有权

    公开(公告)号：US20130092989A1

    公开(公告)日：2013-04-18

    申请号：US13273012

    申请日：2011-10-13

    Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

    Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

    Capacitor formation for a pumping circuit
    7.
    发明授权
    Capacitor formation for a pumping circuit 有权
    泵电路的电容器形成

    公开(公告)号：US08587047B2

    公开(公告)日：2013-11-19

    申请号：US12101161

    申请日：2008-04-11

    Applicant: Yu-Wei Ting ,  Shing-Hwa Renn ,  Yu-Teh Chiang ,  Chung-Ren Li ,  Tieh-Chiang Wu

    Inventor： Yu-Wei Ting ,  Shing-Hwa Renn ,  Yu-Teh Chiang ,  Chung-Ren Li ,  Tieh-Chiang Wu

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L29/66181 ,  H01L28/87

    Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.

    Abstract translation: 用于泵浦电路的电容器结构包括衬底，衬底中的U形底部电极，衬底中的T形顶部电极和设置在U形底部和T形顶部电极之间的介电层。 U形底部电极和T形顶部电极之间的电容器结构的接触面积通过U形底部电极和T形顶部电极的三次接合而延伸。

    Device and method for detecting alignment of active areas and memory cell structures in DRAM devices
    8.
    发明授权
    Device and method for detecting alignment of active areas and memory cell structures in DRAM devices 有权
    用于检测DRAM器件中的有源区和存储单元结构的对准的装置和方法

    公开(公告)号：US07026647B2

    公开(公告)日：2006-04-11

    申请号：US10673310

    申请日：2003-09-29

    Applicant: Tie Jiang Wu ,  Chien-Chang Huang ,  Bo Ching Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

    Inventor： Tie Jiang Wu ,  Chien-Chang Huang ,  Bo Ching Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

    IPC: H01L23/58

    CPC classification number: H01L27/10876 ,  G11C11/401 ,  G11C29/36 ,  G11C2029/5002 ,  H01L22/34 ,  H01L27/10841

    Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

    Abstract translation: 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。

    Test structure of DRAM
    9.
    发明授权
    Test structure of DRAM 有权
    DRAM的测试结构

    公开(公告)号：US06891216B1

    公开(公告)日：2005-05-10

    申请号：US10664163

    申请日：2003-09-17

    Applicant: Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

    Inventor： Chien-Chang Huang ,  Tie-Jiang Wu ,  Chin-Ling Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L31/119 ,  H01L29/76 ,  H01L29/94

    CPC classification number: H01L22/34 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181

    Abstract: A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.

    Abstract translation: DRAM阵列的测试结构包括基板。 晶体管形成在衬底上并且具有第一区域和第二区域作为其源极/漏极区域。 深沟槽电容器形成在与晶体管相邻并且具有第一宽度。 浅沟槽隔离形成在深沟槽电容器的顶部，并且具有第二宽度。 第二宽度基本上比第一宽度短。 第三区域形成为与深沟槽电容器相邻。 第一触点形成在基板上并与第一区域接触。 第二触点形成在基板上并与第三区域接触。

    Test key and method for validating the doping concentration of buried layers within a deep trench capacitors
    10.
    发明授权
    Test key and method for validating the doping concentration of buried layers within a deep trench capacitors 有权
    用于验证深沟槽电容器内掩埋层的掺杂浓度的测试键和方法

    公开(公告)号：US06812487B1

    公开(公告)日：2004-11-02

    申请号：US10601417

    申请日：2003-06-23

    Applicant: Tie-Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang ,  Tse-Main Kuo

    Inventor： Tie-Jiang Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo-Ching Jiang ,  Tse-Main Kuo

    IPC: H01L2358

    CPC classification number: H01L27/10861 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002 ,  H01L22/34 ,  H01L29/66181

    Abstract: A test key for validating the doping concentration of buried layers within a deep trench capacitor. The test key is deposited in the scribe line region of a wafer. In the test key of the present invention, the deep trench capacitor is deposited in the scribe line region and has three buried layers of three doping concentrations. An isolation region is deposited in the capacitor, and a first plug, a second and a third plug are coupled to three positions of one buried layer of the three respectively. The present invention determines whether the doping concentration of buried layers within a deep trench capacitor is valid by a first resistance measured between the first plug and the second plug and a second resistance measured between the second plug and the third plug.

    Abstract translation: 一种用于验证深沟槽电容器内埋层掺杂浓度的测试键。 测试键被沉积在晶片的划线区域中。 在本发明的测试键中，深沟槽电容器沉积在划线区域中并且具有三个掺杂浓度的三个掩埋层。 隔离区域沉积在电容器中，并且第一插头，第二和第三插头分别耦合到三个一个埋层的三个位置。 本发明通过在第一插头和第二插头之间测量的第一电阻以及在第二插头和第三插头之间测量的第二电阻来确定深沟槽电容器内的埋层的掺杂浓度是否有效。

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