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    Capacitor structure for a dynamic random access memory cell
    1.
    发明授权
    Capacitor structure for a dynamic random access memory cell 失效
    动态随机存取存储单元的电容结构

    公开(公告)号：US6027969A

    公开(公告)日：2000-02-22

    申请号：US090497

    申请日：1998-06-04

    Applicant: Kuo Ching Huang ,  James Wu

    Inventor： Kuo Ching Huang ,  James Wu

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10852 ,  H01L27/10817

    Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

    Abstract translation: 已经开发了用于增加DRAM层叠电容器结构的表面积以及因此增加电容的方法。 通过使用多个多晶硅和绝缘体沉积，以及通过使用干各向异性和湿各向同性的蚀刻工艺，创建了包含多晶硅分支的存储节点电极。 在硅氧化物台面的侧面产生的多晶硅间隔物的使用增加了多晶硅分支的垂直分量。 从多晶硅分支之间去除绝缘体层的一部分导致增加的存储节点电极表面积的暴露。 在多晶硅分支之间的绝缘体层的未蚀刻部分为存储节点电极提供由多晶硅分支组成的结构支撑。

    Co-based wire and method for saw tip manufacture and repair
    7.
    发明申请
    Co-based wire and method for saw tip manufacture and repair 审中-公开
    用于锯尖制造和修理的共线电线和方法

    公开(公告)号：US20060210826A1

    公开(公告)日：2006-09-21

    申请号：US11085308

    申请日：2005-03-21

    Applicant: James Wu ,  Heidi de Villiers-Lovelock

    Inventor： James Wu ,  Heidi de Villiers-Lovelock

    IPC: B32B19/00

    CPC classification number: C22C19/07 ,  Y10T428/30

    Abstract: A Co-based alloy, a tubular wire with a Co-based sheath, and a method for forming a saw tip involving an alloy comprising, by approximate weight %, C (0.3-2.4), B (0.1-1.0), Cr (25-35), Mo (4-20), Si (0.1-1.57), Co (Balance), wherein the total concentration of boron and carbon is between about 1.2 wt % and about 2.5 wt % and the Si has a concentration no greater than about (1.8−(0.12[Mo])+(0.1*([B]+[C]))).

    Abstract translation: Co基合金，具有Co基鞘的管状线以及用于形成涉及合金的锯尖的方法，包括以重量％计，C（0.3-2.4），B（0.1-1.0），Cr（ 25-35），Mo（4-20），Si（0.1-1.57），Co（余量），其中硼和碳的总浓度为约1.2重量％至约2.5重量％，Si的浓度为 大于约（1.8-（0.12 [Mo]）+（0.1 *（[B] + [C]）））。

    Shower head
    8.
    外观设计
    Shower head 失效

    公开(公告)号：USD507819S1

    公开(公告)日：2005-07-26

    申请号：US29206727

    申请日：2004-06-01

    Applicant: James Wu

    Designer： James Wu

    Shower head
    9.
    外观设计
    Shower head 失效

    公开(公告)号：USD507037S1

    公开(公告)日：2005-07-05

    申请号：US29202381

    申请日：2004-03-31

    Applicant: James Wu

    Designer： James Wu

    Via array monitor and method of monitoring induced electrical charging
    10.
    发明申请
    Via array monitor and method of monitoring induced electrical charging 失效
    通过阵列监视器和监控感应充电的方法

    公开(公告)号：US20050032253A1

    公开(公告)日：2005-02-10

    申请号：US10634005

    申请日：2003-08-04

    Applicant: Yung-Lung Hsu ,  James Wu

    Inventor： Yung-Lung Hsu ,  James Wu

    IPC: H01L21/66 ,  H01L23/544 ,  H01L21/4763 ,  H01L23/58

    CPC classification number: H01L22/20 ,  H01L22/34 ,  H01L2924/3011 ,  Y10S438/926

    Abstract: An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated dummy metal portions to form a via array monitor; exposing the semiconductor process wafer including the via array monitor to an electrical charge altering process including to produce an electrically charged state over at least a portion of the semiconductor wafer; carrying out electrical measurements of the via array monitor to determine a level of the electrically charged state; and, carrying out an electrically charge neutralizing process to reduce a level of the electrically charged state to a predetermined acceptable level prior to carrying out a subsequent process.

    Abstract translation: 一种电监测器，包括用于确定和减少半导体工艺晶片的带电状态的通孔阵列和方法，所述方法包括提供包括多个散置的电隔离的虚设金属部分的金属填充通孔阵列以形成通孔阵列监视器; 将包括通孔阵列监视器的半导体工艺晶片暴露于电荷改变过程，其包括在半导体晶片的至少一部分上产生带电状态; 执行通孔阵列监视器的电气测量以确定带电状态的水平; 并且进行电荷中和处理，以在执行后续处理之前将带电状态的水平降低到预定的可接受水平。

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