公开(公告)号：US6027969A

公开(公告)日：2000-02-22

申请号：US090497

申请日：1998-06-04

Applicant: Kuo Ching Huang ,  James Wu

Inventor： Kuo Ching Huang ,  James Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

Abstract translation: 已经开发了用于增加DRAM层叠电容器结构的表面积以及因此增加电容的方法。 通过使用多个多晶硅和绝缘体沉积，以及通过使用干各向异性和湿各向同性的蚀刻工艺，创建了包含多晶硅分支的存储节点电极。 在硅氧化物台面的侧面产生的多晶硅间隔物的使用增加了多晶硅分支的垂直分量。 从多晶硅分支之间去除绝缘体层的一部分导致增加的存储节点电极表面积的暴露。 在多晶硅分支之间的绝缘体层的未蚀刻部分为存储节点电极提供由多晶硅分支组成的结构支撑。

公开(公告)号：US6037222A

公开(公告)日：2000-03-14

申请号：US83271

申请日：1998-05-22

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L27/10894 ,  H01L27/1052 ,  H01L27/10873

Abstract: A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises:(a) forming a first gate oxide layer 20, a first polysilicon layer 24, and a first gate cap layer 28 over said logic area 12;(b) forming memory gate structures 34 36 38 40 42A in memory area 14,(c) forming memory LDD regions 50 adjacent to said memory gate structures 24 26 28 40 in said memory area 14;(d) patterning said first gate oxide layer 20, said first polysilicon layer 24 and said first gate cap layer 28 over said logic area forming logic gate structures 20 24A & 20 24B;(e) forming spacers 66;(f) forming logic Source/drain regions 62;(g) using a salicide process to form self-aligned silicide logic S/D contacts 72 to said Source/drain regions 62, and to form self-aligned silicide logic gate contacts 74 to said logic gate structures 20 24B & 20 24A; and(h) forming self aligned polycide contacts 80 to said memory source/drain regions 50.

Abstract translation: 一种制造具有嵌入式逻辑的存储器件的方法。 存储器和逻辑FETs具有两个不同的两个栅极氧化层20 34的厚度。 该方法集成了（1）自杀式接触过程72 74（逻辑器件）和双栅极（N + / P +）逻辑门24A 24B技术与（2）存储器件Polycide与自对准接触80技术。 该方法包括：（a）在所述逻辑区域12上形成第一栅极氧化物层20，第一多晶硅层24和第一栅极覆盖层28; （b）在存储器区域14中形成存储器栅极结构34 36 38 40 42A，（c）在所述存储区域14中形成与所述存储器栅极结构24 26 28 40相邻的存储器LDD区域50; （d）在所述逻辑区域上形成所述第一栅极氧化物层20，所述第一多晶硅层24和所述第一栅极覆盖层28，形成逻辑门结构20A，24A和20BB; （e）形成间隔件66; （f）形成逻辑源极/漏极区域62; （g）使用自对准硅化物工艺将自对准硅化物逻辑S / D触点72形成到所述源极/漏极区62，并且形成到所述逻辑门结构20 24B和20 24A的自对准硅化物逻辑门触点74; 和（h）将自对准的多晶硅触点80形成到所述存储器源极/漏极区50。

公开(公告)号：US5953606A

公开(公告)日：1999-09-14

申请号：US67151

申请日：1998-02-27

Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Cheng-Yeh Shih ,  Dun Nian Yaung

IPC: H01L21/8244 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L27/1108 ,  Y10S257/903

Abstract: A method of forming a contact between a conductor and a substrate region in a MOSFET SRAM starts with forming a dielectric layer on the surface of a partially completed SRAM device with pass and latch transistors covering the transistors. Then, form a thin film gate electrode and an interconnect on the dielectric layer with a gate oxide layer covering the gate electrode and the interconnect; cover the gate oxide layer with a poly conductive layer. Then form a silicon oxide layer over the poly conductive layer and pattern the silicon oxide layer to form a silicon oxide channel mask over the poly conductive layer which is used to pattern the silicon oxide layer into a channel mask over the gate electrode. The channel mask is used for patterning the implanting of dopant into the poly conductive layer aside from the channel mask to form a source region, a drain region and an interconnect in the poly conductive layer. Then form a contact through the gate oxide layer between the interconnect and the poly conductive layer by forming a tungsten layer over the poly conductive layer aside from the channel mask which remains in place.

Abstract translation: 在MOSFET SRAM中形成导体和衬底区域之间的接触的方法开始于在部分完成的SRAM器件的表面上形成覆盖晶体管的通过和锁存晶体管的介质层。 然后，在电介质层上形成薄膜栅电极和互连，其中覆盖栅极和互连的栅氧化层; 用多导电层覆盖栅极氧化层。 然后在多导电层上形成氧化硅层，并对氧化硅层进行图案化以在多晶硅导电层上形成氧化硅沟道掩模，该导电层用于将氧化硅层图案化成栅电极上的沟道掩模。 沟道掩模用于图案化掺杂剂注入到沟道掩模之外的多导电层中以在多导电层中形成源极区域，漏极区域和互连。 然后通过在保持在适当位置的通道掩模之外的多导电层上形成钨层，通过互连和多导电层之间的栅极氧化层形成接触。

公开(公告)号：US06287939B1

公开(公告)日：2001-09-11

申请号：US09216789

申请日：1998-12-21

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC: H01L2176

CPC classification number: H01L21/76224 ,  H01L21/76895

Abstract: The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.

Abstract translation: 本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。 本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。 该过程开始于在半导体衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成氮化物层。 图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。 接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。 填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。 将N 2离子注入填充氧化物区域。 进行退火以形成掩埋的氮氧化物层。 掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。 去除氮化物层。 然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

公开(公告)号：US6080637A

公开(公告)日：2000-06-27

申请号：US206736

申请日：1998-12-07

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a "T" shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.

Abstract translation: 已经开发了在半导体衬底中形成绝缘体填充的浅沟槽的方法，其中浅沟槽中的绝缘体层不暴露于用于移除限定复合绝缘体层的程序。 该工艺的特征是在半导体衬底中产生在厚氮化硅层中用作复合绝缘体层的组分的横向凹槽，其中复合绝缘体层用于随后定义浅沟槽。 在复合绝缘体层中的绝缘体沉积，填充开口和凹陷，以及填充浅沟槽，然后在复合绝缘体层的顶表面上除去多余的绝缘体填充物，导致形成“T”形 绝缘体，由绝缘体形状构成，位于浅沟槽中，并且由更宽的绝缘体形状组成，位于复合绝缘体形状中，侧壁凹陷在厚氮化硅层中，并且具有更宽的绝缘体形状， 绝缘体形状，在浅沟槽。 通过更宽的绝缘体形状，在浅沟槽中的绝缘体被保护以避免用于去除复合绝缘体层的部件的程序。

公开(公告)号：US20100281199A1

公开(公告)日：2010-11-04

申请号：US12433544

申请日：2009-04-30

Applicant: Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

Inventor： Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

IPC: G06F13/00

CPC classification number: G06F13/4068 ,  G06F13/12 ,  G06F13/409 ,  G06F13/4282

Abstract: A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices.

Abstract translation: 数据存储设备载体系统包括被配置为支持一个或多个数据存储设备的载体，包括被配置为与母板电耦合的一个或多个耦合连接器设备的背板以及可操作以将多个数据存储器 载体与背板支持的设备。 在一个实施例中，一个或多个耦合连接器装置可操作以传送通信信号和电力。 插入器板可操作以将电力从背板上的单个端口提供给多个数据存储设备中的每一个。 插入器板还可操作地将背板上的主端口之间的通信信号传送到多个数据存储设备中的第一个，并将背板上的辅助端口之间的通信信号传递到多个 数据存储设备。

公开(公告)号：US6165880A

公开(公告)日：2000-12-26

申请号：US94869

申请日：1998-06-15

Applicant: Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

Inventor： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L21/32053

Abstract: A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

Abstract translation: 实现了对图案化多晶硅层（例如FET的栅电极）进行改进的自对准接触（SAC）的方法。 植入轻掺杂的源极/漏极区域。 沉积第二绝缘层并回蚀刻以形成第一侧壁间隔物。 沉积氮化硅蚀刻停止层和第一多晶硅化硅（IPO1）层。 在IPO1层中蚀刻第一SAC开口到蚀刻停止层，同时蚀刻用于栅电极的开口，从而消除掩模步骤。 在SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，其在接触的BOE清洁期间保护第一侧壁间隔物。 使用图案化的多晶硅化合物层来制造SAC和电互连。 沉积第二个IPO层以提供绝缘，并且沉积层间电介质层。 将第二SAC开口蚀刻到蚀刻停止层以进行下一级金属互连，同时蚀刻到栅电极的接触开口以完成。 在第二SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，以在清洁期间保护第一侧壁间隔物。 金属插塞由第二SAC开口中的第一金属和与栅电极的开口形成。 图案化第二金属以将结构完成到第一级金属互连。

公开(公告)号：US6162686A

公开(公告)日：2000-12-19

申请号：US156362

申请日：1998-09-18

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Yu-Hua Lee ,  Ming-Hsin Li

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Yu-Hua Lee ,  Ming-Hsin Li

IPC: H01L23/525 ,  H01L21/336 ,  H01L21/00 ,  H01L21/331 ,  H01L21/44 ,  H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening. A fourth insulating layer is formed over the plug fuse and the third insulating layer. A fuse opening is formed at least partially though the fourth insulating layer over the fuse area.

Abstract translation: 在通过塞子形成在保护环区域14和产品装置区域中的相同步骤中形成带槽保险丝（插头保险丝）的方法。 本发明的一个关键点是从通孔塞层而不是金属层形成保险丝。 此外，围绕插头形状形成关键保护环。 本发明可以包括：提供具有保险丝区域的半导体结构，围绕保险丝区域的保护环区域; 和设备区域。 形成第一和第二导电条。 第一和第二绝缘层形成在第一和第二导电条上。 插头触点和熔丝插头通过第一和第二绝缘层形成到第一和第二导电条。 在第二绝缘层上形成第三绝缘层。 金属线形成在器件区域中的第三绝缘层上。 在第三绝缘层中形成保险丝通孔。 保险丝通过开口形成插头保险丝。 在插头熔断器和第三绝缘层上形成第四绝缘层。 保险丝开口至少部分地通过保险丝区域上的第四绝缘层形成。

公开(公告)号：US09176915B2

公开(公告)日：2015-11-03

申请号：US12433544

申请日：2009-04-30

Applicant: Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

Inventor： Chi-Chang Fu ,  Kuo Ching Huang ,  Feng-Cheng Su ,  Jason Alan Yelinek

IPC: G06F13/12 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F13/12 ,  G06F13/409 ,  G06F13/4282

Abstract: A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices.

Abstract translation: 数据存储设备载体系统包括被配置为支持一个或多个数据存储设备的载体，包括被配置为与母板电耦合的一个或多个耦合连接器设备的背板以及可操作以将多个数据存储器 载体与背板支持的设备。 在一个实施例中，一个或多个耦合连接器装置可操作以传送通信信号和电力。 插入器板可操作以将电力从背板上的单个端口提供给多个数据存储设备中的每一个。 插入器板还可操作地将背板上的主端口之间的通信信号传送到多个数据存储设备中的第一个，并将背板上的辅助端口之间的通信信号传递到多个 数据存储设备。

公开(公告)号：US06403416B1

公开(公告)日：2002-06-11

申请号：US09226279

申请日：1999-01-07

Applicant: Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

Inventor： Kuo Ching Huang ,  Yu-Hua Lee ,  James (Cheng-Ming) Wu ,  Wen-Chuan Chiang

IPC: H01L218242

CPC classification number: H01L28/91

Abstract: A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.

Abstract translation: 描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。 第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。 沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。 沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。 使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。 沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。 在热磷酸中除去第一和第二Si 3 N 4层。 电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。